First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules

Sachin Yadav; Kian Hua Tan; Annie; Kian Hui Goh; Sujith Subramanian; Kain Lu Low; Nanyan Chen; Bowen Jia; Soon Fatt Yoon; Gengchiau Liang; Xiao Gong; Yee Chia Yeo

doi:10.1109/IEDM.2015.7409612

First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules

Sachin Yadav, Kian Hua Tan, Annie, Kian Hui Goh, Sujith Subramanian, Kain Lu Low, Nanyan Chen, Bowen Jia, Soon Fatt Yoon, Gengchiau Liang, Xiao Gong, Yee Chia Yeo

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

12 Citations (Scopus)

Abstract

The first monolithic integration of Ge p-FETs and InAs n-FETs on silicon substrate using a sub-120 nm III-V buffer technology is reported. A common digital etch process was developed to precisely control the etching of InAs and Ge, enabling the realization of Ge p-FETs and InAs n-FETs with a body thickness T_body of below 5 nm and channel lengths LCH smaller than 200 nm. Other process modules such as common gate stack and contact processes were also employed. By comparing with other reports that co-integrated Si_1-xGe_x p-FETs and In_xGa_1-xAs n-FETs on Si or Ge substrates, the Ge p-FETs and InAs n-FETs in this work achive the highest drive current I_ON.

Original language	English
Title of host publication	2015 IEEE International Electron Devices Meeting, IEDM 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2.3.1-2.3.4
ISBN (Electronic)	9781467398930
DOIs	https://doi.org/10.1109/IEDM.2015.7409612
Publication status	Published - 16 Feb 2015
Externally published	Yes
Event	61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, United States Duration: 7 Dec 2015 → 9 Dec 2015

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2016-February
ISSN (Print)	0163-1918

Conference

Conference	61st IEEE International Electron Devices Meeting, IEDM 2015
Country/Territory	United States
City	Washington
Period	7/12/15 → 9/12/15

Access to Document

10.1109/IEDM.2015.7409612

Cite this

Yadav, S., Tan, K. H., Annie, Goh, K. H., Subramanian, S., Low, K. L., Chen, N., Jia, B., Yoon, S. F., Liang, G., Gong, X., & Yeo, Y. C. (2015). First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules. In 2015 IEEE International Electron Devices Meeting, IEDM 2015 (pp. 2.3.1-2.3.4). Article 7409612 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2015.7409612

Yadav, Sachin ; Tan, Kian Hua ; Annie et al. / First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate : Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules. 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 2.3.1-2.3.4 (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{1669a263e62b46129e79f0f63b8718c7,

title = "First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules",

abstract = "The first monolithic integration of Ge p-FETs and InAs n-FETs on silicon substrate using a sub-120 nm III-V buffer technology is reported. A common digital etch process was developed to precisely control the etching of InAs and Ge, enabling the realization of Ge p-FETs and InAs n-FETs with a body thickness Tbody of below 5 nm and channel lengths LCH smaller than 200 nm. Other process modules such as common gate stack and contact processes were also employed. By comparing with other reports that co-integrated Si1-xGex p-FETs and InxGa1-xAs n-FETs on Si or Ge substrates, the Ge p-FETs and InAs n-FETs in this work achive the highest drive current ION.",

author = "Sachin Yadav and Tan, {Kian Hua} and Annie and Goh, {Kian Hui} and Sujith Subramanian and Low, {Kain Lu} and Nanyan Chen and Bowen Jia and Yoon, {Soon Fatt} and Gengchiau Liang and Xiao Gong and Yeo, {Yee Chia}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 61st IEEE International Electron Devices Meeting, IEDM 2015 ; Conference date: 07-12-2015 Through 09-12-2015",

year = "2015",

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doi = "10.1109/IEDM.2015.7409612",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

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Yadav, S, Tan, KH, Annie, Goh, KH, Subramanian, S, Low, KL, Chen, N, Jia, B, Yoon, SF, Liang, G, Gong, X & Yeo, YC 2015, First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules. in 2015 IEEE International Electron Devices Meeting, IEDM 2015., 7409612, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2016-February, Institute of Electrical and Electronics Engineers Inc., pp. 2.3.1-2.3.4, 61st IEEE International Electron Devices Meeting, IEDM 2015, Washington, United States, 7/12/15. https://doi.org/10.1109/IEDM.2015.7409612

First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules. / Yadav, Sachin; Tan, Kian Hua; Annie et al.
2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 2.3.1-2.3.4 7409612 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

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AU - Yadav, Sachin

AU - Tan, Kian Hua

AU - Annie,

AU - Goh, Kian Hui

AU - Subramanian, Sujith

AU - Low, Kain Lu

AU - Chen, Nanyan

AU - Jia, Bowen

AU - Yoon, Soon Fatt

AU - Liang, Gengchiau

AU - Gong, Xiao

AU - Yeo, Yee Chia

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N2 - The first monolithic integration of Ge p-FETs and InAs n-FETs on silicon substrate using a sub-120 nm III-V buffer technology is reported. A common digital etch process was developed to precisely control the etching of InAs and Ge, enabling the realization of Ge p-FETs and InAs n-FETs with a body thickness Tbody of below 5 nm and channel lengths LCH smaller than 200 nm. Other process modules such as common gate stack and contact processes were also employed. By comparing with other reports that co-integrated Si1-xGex p-FETs and InxGa1-xAs n-FETs on Si or Ge substrates, the Ge p-FETs and InAs n-FETs in this work achive the highest drive current ION.

AB - The first monolithic integration of Ge p-FETs and InAs n-FETs on silicon substrate using a sub-120 nm III-V buffer technology is reported. A common digital etch process was developed to precisely control the etching of InAs and Ge, enabling the realization of Ge p-FETs and InAs n-FETs with a body thickness Tbody of below 5 nm and channel lengths LCH smaller than 200 nm. Other process modules such as common gate stack and contact processes were also employed. By comparing with other reports that co-integrated Si1-xGex p-FETs and InxGa1-xAs n-FETs on Si or Ge substrates, the Ge p-FETs and InAs n-FETs in this work achive the highest drive current ION.

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T3 - Technical Digest - International Electron Devices Meeting, IEDM

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PB - Institute of Electrical and Electronics Engineers Inc.

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ER -

Yadav S, Tan KH, Annie, Goh KH, Subramanian S, Low KL et al. First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules. In 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 2.3.1-2.3.4. 7409612. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2015.7409612

First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules

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