A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor

Sheng Luo; Kain Lu Low; Xiaoyi Zhang; Qianyu Zhao; Hsin Lin; Gengchiau Liang

doi:10.1109/EDTM.2017.7947510

A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor

Sheng Luo^*, Kain Lu Low, Xiaoyi Zhang, Qianyu Zhao, Hsin Lin, Gengchiau Liang

^*Corresponding author for this work

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

1 Citation (Scopus)

Abstract

A comprehensive and rigorous computational study at atomic level was performed for various vertical tunneling field-effect transistor (VTFET) structures based on III-V and two-dimensional (2D) materials. The key challenges of VTFETs were found to be induced by device structures and the channel materials' properties. An optimized VTFET structure was proposed to suppress the parasitic tunneling current and improve subthreshold region performance. A drive current ∼421.6μA/μm is obtained based on the structural-optimized MoS₂-WSe₂ VTFET.

Original language	English
Title of host publication	2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	70-71
Number of pages	2
ISBN (Electronic)	9781509046591
DOIs	https://doi.org/10.1109/EDTM.2017.7947510
Publication status	Published - 13 Jun 2017
Externally published	Yes
Event	2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Toyama, Japan Duration: 28 Feb 2017 → 2 Mar 2017

Publication series

Name	2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings

Conference

Conference	2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017
Country/Territory	Japan
City	Toyama
Period	28/02/17 → 2/03/17

Access to Document

10.1109/EDTM.2017.7947510

Cite this

Luo, S., Low, K. L., Zhang, X., Zhao, Q., Lin, H., & Liang, G. (2017). A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor. In 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings (pp. 70-71). Article 7947510 (2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDTM.2017.7947510

Luo, Sheng ; Low, Kain Lu ; Zhang, Xiaoyi et al. / A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor. 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 70-71 (2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings).

@inproceedings{b5a2460cbf784661be59f640ab336be0,

title = "A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor",

abstract = "A comprehensive and rigorous computational study at atomic level was performed for various vertical tunneling field-effect transistor (VTFET) structures based on III-V and two-dimensional (2D) materials. The key challenges of VTFETs were found to be induced by device structures and the channel materials' properties. An optimized VTFET structure was proposed to suppress the parasitic tunneling current and improve subthreshold region performance. A drive current ∼421.6μA/μm is obtained based on the structural-optimized MoS2-WSe2 VTFET.",

author = "Sheng Luo and Low, {Kain Lu} and Xiaoyi Zhang and Qianyu Zhao and Hsin Lin and Gengchiau Liang",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 ; Conference date: 28-02-2017 Through 02-03-2017",

year = "2017",

month = jun,

day = "13",

doi = "10.1109/EDTM.2017.7947510",

language = "English",

series = "2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "70--71",

booktitle = "2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings",

}

Luo, S, Low, KL, Zhang, X, Zhao, Q, Lin, H & Liang, G 2017, A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor. in 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings., 7947510, 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 70-71, 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017, Toyama, Japan, 28/02/17. https://doi.org/10.1109/EDTM.2017.7947510

A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor. / Luo, Sheng; Low, Kain Lu; Zhang, Xiaoyi et al.
2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 70-71 7947510 (2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

TY - GEN

T1 - A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor

AU - Luo, Sheng

AU - Low, Kain Lu

AU - Zhang, Xiaoyi

AU - Zhao, Qianyu

AU - Lin, Hsin

AU - Liang, Gengchiau

PY - 2017/6/13

Y1 - 2017/6/13

N2 - A comprehensive and rigorous computational study at atomic level was performed for various vertical tunneling field-effect transistor (VTFET) structures based on III-V and two-dimensional (2D) materials. The key challenges of VTFETs were found to be induced by device structures and the channel materials' properties. An optimized VTFET structure was proposed to suppress the parasitic tunneling current and improve subthreshold region performance. A drive current ∼421.6μA/μm is obtained based on the structural-optimized MoS2-WSe2 VTFET.

AB - A comprehensive and rigorous computational study at atomic level was performed for various vertical tunneling field-effect transistor (VTFET) structures based on III-V and two-dimensional (2D) materials. The key challenges of VTFETs were found to be induced by device structures and the channel materials' properties. An optimized VTFET structure was proposed to suppress the parasitic tunneling current and improve subthreshold region performance. A drive current ∼421.6μA/μm is obtained based on the structural-optimized MoS2-WSe2 VTFET.

UR - http://www.scopus.com/inward/record.url?scp=85021899483&partnerID=8YFLogxK

U2 - 10.1109/EDTM.2017.7947510

DO - 10.1109/EDTM.2017.7947510

M3 - Conference Proceeding

AN - SCOPUS:85021899483

T3 - 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings

SP - 70

EP - 71

BT - 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017

Y2 - 28 February 2017 through 2 March 2017

ER -

Luo S, Low KL, Zhang X, Zhao Q, Lin H, Liang G. A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor. In 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 70-71. 7947510. (2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings). doi: 10.1109/EDTM.2017.7947510

A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor

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