Modeling and verification of NCL circuits using PAT

NULL Conventional Logic (NCL) is a Delay-Insensitive (DI) clockless paradigm and is suitable for implementing asynchronous circuits. Efficient methods of analysis are required to specify and verify such DI systems. Based on Delay Insensitive sequential Process (DISP) specification, this paper demonstrates the application of formal methods by applying Process Analysis Toolkit (PAT) to model and verify the behavior of NCL circuits. A few useful constructs are successfully modeled and verified by using PAT. The flexibility and simplicity of the coding, simulation and verification shows that PAT is effective and applicable for NCL circuit design and verification.