Abstract
We report on the implementation of an IP core for Pairing-based cryptography. The core performs an elliptic curve cryptographic operation called the Tate Pairing over the field GF(2251). In this paper, we describe the implementation of the design in TSMC 65nm GP CMOS standard cells and the optimisations made for low-power operation. The resulting core computes the pairing in 1.5ms and consumes less than 4mW.
Original language | English |
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Title of host publication | Proceedings - IEEE International SOC Conference, SOCC 2009 |
Pages | 369-372 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2009 |
Externally published | Yes |
Event | IEEE International SOC Conference, SOCC 2009 - Belfast, Ireland Duration: 9 Sept 2009 → 11 Sept 2009 |
Publication series
Name | Proceedings - IEEE International SOC Conference, SOCC 2009 |
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Conference
Conference | IEEE International SOC Conference, SOCC 2009 |
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Country/Territory | Ireland |
City | Belfast |
Period | 9/09/09 → 11/09/09 |
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English, T., Keller, M., Man, K. L., Popovici, E., Schellekens, M., & Marnane, W. (2009). A low-power pairing-based cryptographic accelerator for embedded security applications. In Proceedings - IEEE International SOC Conference, SOCC 2009 (pp. 369-372). Article 5398017 (Proceedings - IEEE International SOC Conference, SOCC 2009). https://doi.org/10.1109/SOCCON.2009.5398017