@inproceedings{6b7a9ae2ff714e1498c9919c4984dc65,
title = "Voltage step stress: A technique for reducing test time of device ageing",
abstract = "Device ageing leads to circuit malfunction and must be controlled. During ageing, defects build up slowly and the test is time consuming and costly. The typical ageing tests are repeated 5 times under different voltages. To reduce the test time, the voltage step stress (VSS) technique is proposed, which replaces the multiple tests under different voltage by a single test and saves time. This paper reviews the recent development of the VSS technique. After presenting its underlying principle, its applicability will be demonstrated for both the negative bias temperature instability and hot carrier ageing.",
keywords = "Ageing, Defects, Degradation, Hot carriers, Instabilities, Lifetime, NBTI",
author = "Zhang, {J. F.} and Z. Ji and M. Duan and W. Zhang and Zhao, {C. Z.}",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 17th IEEE International Conference on IC Design and Technology, ICICDT 2019 ; Conference date: 17-06-2019 Through 19-06-2019",
year = "2019",
month = jun,
doi = "10.1109/ICICDT.2019.8790938",
language = "English",
series = "17th IEEE International Conference on IC Design and Technology, ICICDT 2019 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "17th IEEE International Conference on IC Design and Technology, ICICDT 2019 - Proceedings",
}