Towards a language based synthesis of NCL circuits

This paper is an attempt to provide a language front-end to synthesise asynchronous control circuits using NCL technology. The target implementation being delay insensitive (DI), the specification language should be DI as well. Delay Insensitive Sequential Processes (DISP) is a process algebra where the behaviour of asynchronous control logic blocks is expressed by the processes. We show that one can confine the orphan paths in an NCL implementation by decomposing the language expressions. A few basic DISP constructs have been successfully mapped to NCL and small cases studies performed. This is a step towards an alternative synthesis path for NCL circuits.