Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process

Chun Zhao; W. Zhang; C. Z. Zhao; K. L. Man; T. T. Jeong; J. K. Seon; Y. Lee

doi:10.1109/isocc.2011.6138771

Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process

Chun Zhao, W. Zhang, C. Z. Zhao, K. L. Man, T. T. Jeong, J. K. Seon, Y. Lee

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

4 Citations (Scopus)

Abstract

The Application Specific Integrated Circuit (ASIC) design approach depends highly on the quality of the cell library to meet design specifications. Due to the use of both digital and analog signal processing, mixed-signal integrated circuits library are usually designed for specific purposes and the related design requires a high level of expertise and careful use of computer aided design tools. The paper establishes a series of standard cell: scan D flip-flops based on 0.5 micron complementary metal oxide semiconductor mixed-signal process. The research work presented in this paper includes reverse engineering, standard cell schematic and symbol building, standard cell layout drawing and post layout simulation.

Original language	English
Title of host publication	2011 International SoC Design Conference, ISOCC 2011
Publisher	IEEE Computer Society
Pages	306-309
Number of pages	4
ISBN (Print)	9781457707100
DOIs	https://doi.org/10.1109/isocc.2011.6138771
Publication status	Published - 2011
Event	8th International SoC Design Conference 2011, ISOCC 2011 - Jeju, Korea, Republic of Duration: 17 Nov 2011 → 18 Nov 2011

Publication series

Name	2011 International SoC Design Conference, ISOCC 2011

Conference

Conference	8th International SoC Design Conference 2011, ISOCC 2011
Country/Territory	Korea, Republic of
City	Jeju
Period	17/11/11 → 18/11/11

Keywords

IC design
Layout
Scan D flip-flops
Standard cell libray
Tanner EDA tools

Access to Document

10.1109/isocc.2011.6138771

Cite this

Zhao, C., Zhang, W., Zhao, C. Z., Man, K. L., Jeong, T. T., Seon, J. K., & Lee, Y. (2011). Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process. In 2011 International SoC Design Conference, ISOCC 2011 (pp. 306-309). (2011 International SoC Design Conference, ISOCC 2011). IEEE Computer Society. https://doi.org/10.1109/isocc.2011.6138771

@inproceedings{d7f93ce02b3149f5807d0757d5b0db94,

title = "Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process",

abstract = "The Application Specific Integrated Circuit (ASIC) design approach depends highly on the quality of the cell library to meet design specifications. Due to the use of both digital and analog signal processing, mixed-signal integrated circuits library are usually designed for specific purposes and the related design requires a high level of expertise and careful use of computer aided design tools. The paper establishes a series of standard cell: scan D flip-flops based on 0.5 micron complementary metal oxide semiconductor mixed-signal process. The research work presented in this paper includes reverse engineering, standard cell schematic and symbol building, standard cell layout drawing and post layout simulation.",

keywords = "IC design, Layout, Scan D flip-flops, Standard cell libray, Tanner EDA tools",

author = "Chun Zhao and W. Zhang and Zhao, {C. Z.} and Man, {K. L.} and Jeong, {T. T.} and Seon, {J. K.} and Y. Lee",

year = "2011",

doi = "10.1109/isocc.2011.6138771",

language = "English",

isbn = "9781457707100",

series = "2011 International SoC Design Conference, ISOCC 2011",

publisher = "IEEE Computer Society",

pages = "306--309",

booktitle = "2011 International SoC Design Conference, ISOCC 2011",

note = "8th International SoC Design Conference 2011, ISOCC 2011 ; Conference date: 17-11-2011 Through 18-11-2011",

}

Zhao, C, Zhang, W, Zhao, CZ, Man, KL, Jeong, TT, Seon, JK & Lee, Y 2011, Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process. in 2011 International SoC Design Conference, ISOCC 2011. 2011 International SoC Design Conference, ISOCC 2011, IEEE Computer Society, pp. 306-309, 8th International SoC Design Conference 2011, ISOCC 2011, Jeju, Korea, Republic of, 17/11/11. https://doi.org/10.1109/isocc.2011.6138771

Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process. / Zhao, Chun; Zhang, W.; Zhao, C. Z. et al.
2011 International SoC Design Conference, ISOCC 2011. IEEE Computer Society, 2011. p. 306-309 (2011 International SoC Design Conference, ISOCC 2011).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

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AU - Zhao, Chun

AU - Zhang, W.

AU - Zhao, C. Z.

AU - Man, K. L.

AU - Jeong, T. T.

AU - Seon, J. K.

AU - Lee, Y.

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AB - The Application Specific Integrated Circuit (ASIC) design approach depends highly on the quality of the cell library to meet design specifications. Due to the use of both digital and analog signal processing, mixed-signal integrated circuits library are usually designed for specific purposes and the related design requires a high level of expertise and careful use of computer aided design tools. The paper establishes a series of standard cell: scan D flip-flops based on 0.5 micron complementary metal oxide semiconductor mixed-signal process. The research work presented in this paper includes reverse engineering, standard cell schematic and symbol building, standard cell layout drawing and post layout simulation.

KW - IC design

KW - Layout

KW - Scan D flip-flops

KW - Standard cell libray

KW - Tanner EDA tools

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ER -

Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process

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Keywords

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