Process algebraic approach to SystemVerilog

K. L. Man; M. Boubekeur; M. P. Schellekens

doi:10.1109/CCECE.2007.29

Process algebraic approach to SystemVerilog

K. L. Man, M. Boubekeur, M. P. Schellekens

University College Cork

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

5 Citations (Scopus)

Abstract

We develop a process algebraic framework, called process algebraic framework for IEEE 1800™ SystemVerilog (PAFSV), for formal specification and analysis of IEEE 1800™ SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a labelled transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800™ SystemVerilog. This paper serves as an introduction of PAFSV to architects, engineers and researchers from the electronic design community.

Original language	English
Title of host publication	2007 Canadian Conference on Electrical and Computer Engineering, CCECD
Pages	86-89
Number of pages	4
DOIs	https://doi.org/10.1109/CCECE.2007.29
Publication status	Published - 2007
Externally published	Yes
Event	2007 Canadian Conference on Electrical and Computer Engineering, CCECD - Vancouver, BC, Canada Duration: 22 Apr 2007 → 26 Apr 2007

Publication series

Name	Canadian Conference on Electrical and Computer Engineering
ISSN (Print)	0840-7789

Conference

Conference	2007 Canadian Conference on Electrical and Computer Engineering, CCECD
Country/Territory	Canada
City	Vancouver, BC
Period	22/04/07 → 26/04/07

Access to Document

10.1109/CCECE.2007.29

Cite this

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title = "Process algebraic approach to SystemVerilog",

abstract = "We develop a process algebraic framework, called process algebraic framework for IEEE 1800{\texttrademark} SystemVerilog (PAFSV), for formal specification and analysis of IEEE 1800{\texttrademark} SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a labelled transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800{\texttrademark} SystemVerilog. This paper serves as an introduction of PAFSV to architects, engineers and researchers from the electronic design community.",

author = "Man, {K. L.} and M. Boubekeur and Schellekens, {M. P.}",

year = "2007",

doi = "10.1109/CCECE.2007.29",

language = "English",

isbn = "1424410215",

series = "Canadian Conference on Electrical and Computer Engineering",

pages = "86--89",

booktitle = "2007 Canadian Conference on Electrical and Computer Engineering, CCECD",

note = "2007 Canadian Conference on Electrical and Computer Engineering, CCECD ; Conference date: 22-04-2007 Through 26-04-2007",

}

Man, KL, Boubekeur, M & Schellekens, MP 2007, Process algebraic approach to SystemVerilog. in 2007 Canadian Conference on Electrical and Computer Engineering, CCECD., 4232688, Canadian Conference on Electrical and Computer Engineering, pp. 86-89, 2007 Canadian Conference on Electrical and Computer Engineering, CCECD, Vancouver, BC, Canada, 22/04/07. https://doi.org/10.1109/CCECE.2007.29

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AU - Boubekeur, M.

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PY - 2007

Y1 - 2007

N2 - We develop a process algebraic framework, called process algebraic framework for IEEE 1800™ SystemVerilog (PAFSV), for formal specification and analysis of IEEE 1800™ SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a labelled transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800™ SystemVerilog. This paper serves as an introduction of PAFSV to architects, engineers and researchers from the electronic design community.

AB - We develop a process algebraic framework, called process algebraic framework for IEEE 1800™ SystemVerilog (PAFSV), for formal specification and analysis of IEEE 1800™ SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a labelled transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800™ SystemVerilog. This paper serves as an introduction of PAFSV to architects, engineers and researchers from the electronic design community.

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U2 - 10.1109/CCECE.2007.29

DO - 10.1109/CCECE.2007.29

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BT - 2007 Canadian Conference on Electrical and Computer Engineering, CCECD

T2 - 2007 Canadian Conference on Electrical and Computer Engineering, CCECD

Y2 - 22 April 2007 through 26 April 2007

ER -

Process algebraic approach to SystemVerilog

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