PAFSV: A process algebraic framework for systemVerilog

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

3 Citations (Scopus)

Abstract

We develop a process algebraic framework, called process algebraic framework for IEEE 1800™ SystemVerilog (PAFSV), for formal specification and analysis of IEEE 1800™ SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a time transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800™ SystemVerilog. To show that PAFSV is useful for the formal specification and analysis of IEEE 1800™ SystemVerilog designs, we illustrate the use of PAFSV with some examples: A MUX, a synchronous reset D flip-flop and an arbiter.

Original languageEnglish
Title of host publicationProceedings of the International Multiconference on Computer Science and Information Technology, IMCSIT 2008
Pages535-542
Number of pages8
DOIs
Publication statusPublished - 2008
Externally publishedYes
EventInternational Multiconference on Computer Science and Information Technology, IMCSIT 2008 - Wisla, Poland
Duration: 20 Oct 200822 Oct 2008

Publication series

NameProceedings of the International Multiconference on Computer Science and Information Technology, IMCSIT 2008
Volume3

Conference

ConferenceInternational Multiconference on Computer Science and Information Technology, IMCSIT 2008
Country/TerritoryPoland
CityWisla
Period20/10/0822/10/08

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