TY - GEN
T1 - Mathematical modelling of digital hardware systems in timed Chi
AU - Man, K. L.
AU - Schellekens, M. P.
PY - 2007
Y1 - 2007
N2 - Timed Chi (χ) is a timed process algebra, designed for modelling, simulation, verification and real-time control. Its application domain consists of large and complex manufacturing systems. The straightforward syntax and semantics is also highly suited to architects, engineers and researchers from the hardware design community. Since timed Chi is a well-developed algebraic theory from the field of process algebras with timing, we have the idea that timed Chi is also well-suited for addressing various aspects of digital hardware systems (discrete-time systems by nature). To show that timed Chi is useful for mathematical modelling and analysis of digital hardware systems and our idea is correct, we illustrate the use of timed Chi with some benchmark examples of digital hardware systems: a D flip-flop and an asynchronous arbiter.
AB - Timed Chi (χ) is a timed process algebra, designed for modelling, simulation, verification and real-time control. Its application domain consists of large and complex manufacturing systems. The straightforward syntax and semantics is also highly suited to architects, engineers and researchers from the hardware design community. Since timed Chi is a well-developed algebraic theory from the field of process algebras with timing, we have the idea that timed Chi is also well-suited for addressing various aspects of digital hardware systems (discrete-time systems by nature). To show that timed Chi is useful for mathematical modelling and analysis of digital hardware systems and our idea is correct, we illustrate the use of timed Chi with some benchmark examples of digital hardware systems: a D flip-flop and an asynchronous arbiter.
KW - Digital hardware systems
KW - Discrete-time systems
KW - Mathematical analysis
KW - Mathematical modelling
KW - Process algebras
UR - http://www.scopus.com/inward/record.url?scp=56249119913&partnerID=8YFLogxK
M3 - Conference Proceeding
AN - SCOPUS:56249119913
SN - 9780889866331
T3 - Proceedings of the IASTED International Conference on Modelling, Identification, and Control, MIC
SP - 363
EP - 368
BT - Proceedings of the 26th IASTED International Conference on Modelling, Identification, and Control, MIC 2007
T2 - 26th IASTED International Conference on Modelling, Identification, and Control, MIC 2007
Y2 - 12 February 2007 through 14 February 2007
ER -