Investigation of Anomalous Hysteresis in MOS Devices with ZrO₂ Gate Dielectrics

Abnormal capacitance-voltage (CV) behavior is observed in metal-oxide semiconductor devices with zirconium oxide-gate dielectrics using a pulse CV technique. The relative positions of forward and reverse CV traces measured by the pulse technique are opposite those by conventional CV measurement. This unusual phenomenon is inconsistent with charge trapping and de-trapping, but may be mainly attributable to the interface dipoles at the high-k/SiO_x interface. This anomaly is sensitive to growth temperature as well as the post-deposition annealing process. Lower deposition temperature leads to more interface dipoles. However, after annealing in either nitrogen or forming gas ambient, the relative positions of forward and reverse CV curves measured by the pulse technique are consistent with those obtained by conventional CV measurement.