Impact of the Resistive Silicon Base Wafer on Substrate Coupling in Power Integrated Circuits in GaN-on-Si Technology

We report a computational investigation into substrate coupling in power integrated circuits (ICs) in GaN-on-Si technology. Three-dimensional (3D) electromagnetic (EM) simulations have been performed to solve EM fields numerically. S-parameter results in addition to the electric field intensity distribution have been obtained to investigate the impact of the resistive silicon (Si) base wafer on the substrate coupling in GaN-on-Si technology. Various parameters including the conductivity and thickness of the resistive Si substrate as well as the GaN buffer layer have been adopted in the 3D EM simulations. The substrate coupling is found to be relatively small below 10 MHz but become non-negligible at high frequencies (with \vert S 21 vert =- 53 dB at 100 MHz). The EM coupling is mainly through the top GaN buffer layer rather than the resistive Si substrate underneath. The use of resistive Si base wafers of different thickness and conductivity values provide only slight improvement in the substrate coupling. Decreasing the conductivity of the GaN buffer layer is more helpful in the reduction of the substrate coupling by about 20 dB to 60 dB for vert S 21 vert at all simulated frequencies from 1 to 100 MHz.