Highly resilient minimal path routing algorithm for fault tolerant Network-on-Chips

Ka Lok Man; Karthik Yedluri; Hemangee K. Kapoor; Chi Un Lei; Eng Gee Lim; Jieming Ma

doi:10.1016/j.proeng.2011.08.638

Highly resilient minimal path routing algorithm for fault tolerant Network-on-Chips

Ka Lok Man, Karthik Yedluri, Hemangee K. Kapoor, Chi Un Lei, Eng Gee Lim, Jieming Ma^*

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

1 Citation (Scopus)

Abstract

We develop a routing algorithm for fault tolerant 2-D mesh Network-on-Chips (NoCs) with permanent faults. The proposed approach is adaptive and distributed, and does not require extra circuitry or routing tables for fault tolerance operation. Deadlock handling and multiple hop links checking are included for a robust system operation. We demonstrate the algorithm mechanism using a mesh example.

Original language	English
Pages (from-to)	3406-3410
Number of pages	5
Journal	Procedia Engineering
Volume	15
DOIs	https://doi.org/10.1016/j.proeng.2011.08.638
Publication status	Published - 2011
Event	2011 International Conference on Advanced in Control Engineering and Information Science, CEIS 2011 - Dali, Yunnam, China Duration: 18 Aug 2011 → 19 Aug 2011

Keywords

Fault tolerant
Network-on-Chips
Routing

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10.1016/j.proeng.2011.08.638

Cite this

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title = "Highly resilient minimal path routing algorithm for fault tolerant Network-on-Chips",

abstract = "We develop a routing algorithm for fault tolerant 2-D mesh Network-on-Chips (NoCs) with permanent faults. The proposed approach is adaptive and distributed, and does not require extra circuitry or routing tables for fault tolerance operation. Deadlock handling and multiple hop links checking are included for a robust system operation. We demonstrate the algorithm mechanism using a mesh example.",

keywords = "Fault tolerant, Network-on-Chips, Routing",

author = "Man, {Ka Lok} and Karthik Yedluri and Kapoor, {Hemangee K.} and Lei, {Chi Un} and Lim, {Eng Gee} and Jieming Ma",

year = "2011",

doi = "10.1016/j.proeng.2011.08.638",

language = "English",

volume = "15",

pages = "3406--3410",

journal = "Procedia Engineering",

note = "2011 International Conference on Advanced in Control Engineering and Information Science, CEIS 2011 ; Conference date: 18-08-2011 Through 19-08-2011",

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T1 - Highly resilient minimal path routing algorithm for fault tolerant Network-on-Chips

AU - Man, Ka Lok

AU - Yedluri, Karthik

AU - Kapoor, Hemangee K.

AU - Lei, Chi Un

AU - Lim, Eng Gee

AU - Ma, Jieming

PY - 2011

Y1 - 2011

N2 - We develop a routing algorithm for fault tolerant 2-D mesh Network-on-Chips (NoCs) with permanent faults. The proposed approach is adaptive and distributed, and does not require extra circuitry or routing tables for fault tolerance operation. Deadlock handling and multiple hop links checking are included for a robust system operation. We demonstrate the algorithm mechanism using a mesh example.

AB - We develop a routing algorithm for fault tolerant 2-D mesh Network-on-Chips (NoCs) with permanent faults. The proposed approach is adaptive and distributed, and does not require extra circuitry or routing tables for fault tolerance operation. Deadlock handling and multiple hop links checking are included for a robust system operation. We demonstrate the algorithm mechanism using a mesh example.

KW - Fault tolerant

KW - Network-on-Chips

KW - Routing

UR - http://www.scopus.com/inward/record.url?scp=84055178560&partnerID=8YFLogxK

U2 - 10.1016/j.proeng.2011.08.638

DO - 10.1016/j.proeng.2011.08.638

M3 - Conference article

AN - SCOPUS:84055178560

VL - 15

SP - 3406

EP - 3410

JO - Procedia Engineering

JF - Procedia Engineering

T2 - 2011 International Conference on Advanced in Control Engineering and Information Science, CEIS 2011

Y2 - 18 August 2011 through 19 August 2011

ER -

Highly resilient minimal path routing algorithm for fault tolerant Network-on-Chips

Abstract

Keywords

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