High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology

Jieming Ma; Ka Lok Man; Nan Zhang; Sheng Uei Guan; Taikyeong Ted Jeong

doi:10.1117/12.2014353

High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology

Jieming Ma, Ka Lok Man, Nan Zhang, Sheng Uei Guan, Taikyeong Ted Jeong

University of Liverpool

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

2 Citations (Scopus)

Abstract

Estimating arithmetic is a design paradigm for DSP hardware. By allowing structurally incomplete arithmetic circuits to occasionally perform imprecise calculations, higher performance can be achieved in many different electronic systems. By means of approximate compressor design and bottom-up tree topology, this paper presents a novel approach of implementing high-speed, area-efficient and power-aware multipliers. Experimental results are given to show the applicability and effectiveness of our proposed approach.

Original language	English
Title of host publication	Fifth International Conference on Machine Vision, ICMV 2012
Subtitle of host publication	Algorithms, Pattern Recognition and Basic Technologies
Publisher	SPIE
ISBN (Print)	9780819495884
DOIs	https://doi.org/10.1117/12.2014353
Publication status	Published - 2013
Event	2012 5th International Conference on Machine Vision: Algorithms, Pattern Recognition and Basic Technologies, ICMV 2012 - Wuhan, China Duration: 20 Oct 2012 → 21 Oct 2012

Publication series

Name	Proceedings of SPIE - The International Society for Optical Engineering
Volume	8784
ISSN (Print)	0277-786X
ISSN (Electronic)	1996-756X

Conference

Conference	2012 5th International Conference on Machine Vision: Algorithms, Pattern Recognition and Basic Technologies, ICMV 2012
Country/Territory	China
City	Wuhan
Period	20/10/12 → 21/10/12

Keywords

compressors
computer arithmetic
estimating arithmetic
multipliers

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10.1117/12.2014353

Cite this

Ma, J., Man, K. L., Zhang, N., Guan, S. U., & Jeong, T. T. (2013). High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology. In Fifth International Conference on Machine Vision, ICMV 2012: Algorithms, Pattern Recognition and Basic Technologies Article 87841Z (Proceedings of SPIE - The International Society for Optical Engineering; Vol. 8784). SPIE. https://doi.org/10.1117/12.2014353

Ma, Jieming ; Man, Ka Lok ; Zhang, Nan et al. / High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology. Fifth International Conference on Machine Vision, ICMV 2012: Algorithms, Pattern Recognition and Basic Technologies. SPIE, 2013. (Proceedings of SPIE - The International Society for Optical Engineering).

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title = "High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology",

abstract = "Estimating arithmetic is a design paradigm for DSP hardware. By allowing structurally incomplete arithmetic circuits to occasionally perform imprecise calculations, higher performance can be achieved in many different electronic systems. By means of approximate compressor design and bottom-up tree topology, this paper presents a novel approach of implementing high-speed, area-efficient and power-aware multipliers. Experimental results are given to show the applicability and effectiveness of our proposed approach.",

keywords = "compressors, computer arithmetic, estimating arithmetic, multipliers",

author = "Jieming Ma and Man, {Ka Lok} and Nan Zhang and Guan, {Sheng Uei} and Jeong, {Taikyeong Ted}",

year = "2013",

doi = "10.1117/12.2014353",

language = "English",

isbn = "9780819495884",

series = "Proceedings of SPIE - The International Society for Optical Engineering",

publisher = "SPIE",

booktitle = "Fifth International Conference on Machine Vision, ICMV 2012",

note = "2012 5th International Conference on Machine Vision: Algorithms, Pattern Recognition and Basic Technologies, ICMV 2012 ; Conference date: 20-10-2012 Through 21-10-2012",

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Ma, J , Man, KL, Zhang, N, Guan, SU & Jeong, TT 2013, High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology. in Fifth International Conference on Machine Vision, ICMV 2012: Algorithms, Pattern Recognition and Basic Technologies., 87841Z, Proceedings of SPIE - The International Society for Optical Engineering, vol. 8784, SPIE, 2012 5th International Conference on Machine Vision: Algorithms, Pattern Recognition and Basic Technologies, ICMV 2012, Wuhan, China, 20/10/12. https://doi.org/10.1117/12.2014353

High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology. / Ma, Jieming ; Man, Ka Lok; Zhang, Nan et al.
Fifth International Conference on Machine Vision, ICMV 2012: Algorithms, Pattern Recognition and Basic Technologies. SPIE, 2013. 87841Z (Proceedings of SPIE - The International Society for Optical Engineering; Vol. 8784).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

TY - GEN

T1 - High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology

AU - Ma, Jieming

AU - Man, Ka Lok

AU - Zhang, Nan

AU - Guan, Sheng Uei

AU - Jeong, Taikyeong Ted

PY - 2013

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N2 - Estimating arithmetic is a design paradigm for DSP hardware. By allowing structurally incomplete arithmetic circuits to occasionally perform imprecise calculations, higher performance can be achieved in many different electronic systems. By means of approximate compressor design and bottom-up tree topology, this paper presents a novel approach of implementing high-speed, area-efficient and power-aware multipliers. Experimental results are given to show the applicability and effectiveness of our proposed approach.

AB - Estimating arithmetic is a design paradigm for DSP hardware. By allowing structurally incomplete arithmetic circuits to occasionally perform imprecise calculations, higher performance can be achieved in many different electronic systems. By means of approximate compressor design and bottom-up tree topology, this paper presents a novel approach of implementing high-speed, area-efficient and power-aware multipliers. Experimental results are given to show the applicability and effectiveness of our proposed approach.

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KW - computer arithmetic

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DO - 10.1117/12.2014353

M3 - Conference Proceeding

AN - SCOPUS:84879779518

SN - 9780819495884

T3 - Proceedings of SPIE - The International Society for Optical Engineering

BT - Fifth International Conference on Machine Vision, ICMV 2012

PB - SPIE

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Y2 - 20 October 2012 through 21 October 2012

ER -

Ma J , Man KL, Zhang N, Guan SU, Jeong TT. High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology. In Fifth International Conference on Machine Vision, ICMV 2012: Algorithms, Pattern Recognition and Basic Technologies. SPIE. 2013. 87841Z. (Proceedings of SPIE - The International Society for Optical Engineering). doi: 10.1117/12.2014353

High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology

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