TY - GEN
T1 - Design of a reliable XOR-XNOR circuit for arithmetic logic units
AU - Karmani, Mouna
AU - Khedhiri, Chiraz
AU - Hamdi, Belgacem
AU - Rahmani, Amir Mohammad
AU - Man, Ka Lok
AU - Wan, Kaiyu
PY - 2012
Y1 - 2012
N2 - Computer systems used in safety-critical applications like space, avionic and biomedical applications require high reliable integrated circuits (ICs) to ensure the accuracy of data they process. As Arithmetic Logic Units (ALUs) are essential element of computers, designing reliable ALUs is becoming an appropriate strategy to design fault-tolerant computers. In fact, with the continuous increase of integration densities and complexities ICs are susceptible to many modes of failure. Thereby, Reliable operation of ALUs is critical for high performance safety-critical computers. Given that XOR-XNOR circuits are basic building blocks in ALUs, designing efficient reliable XOR-XNOR gates is an important challenge in the area of high performance computers. The reliability enhancement technique presented in this work is based on using a Concurrent Error Detection (CED) based reliable XOR-XNOR circuit implementation to detect permanent and transient faults in ALUs during normal operation in order to improve the reliability of highly critical computer systems. The proposed design is performed using the 32 nm process technology.
AB - Computer systems used in safety-critical applications like space, avionic and biomedical applications require high reliable integrated circuits (ICs) to ensure the accuracy of data they process. As Arithmetic Logic Units (ALUs) are essential element of computers, designing reliable ALUs is becoming an appropriate strategy to design fault-tolerant computers. In fact, with the continuous increase of integration densities and complexities ICs are susceptible to many modes of failure. Thereby, Reliable operation of ALUs is critical for high performance safety-critical computers. Given that XOR-XNOR circuits are basic building blocks in ALUs, designing efficient reliable XOR-XNOR gates is an important challenge in the area of high performance computers. The reliability enhancement technique presented in this work is based on using a Concurrent Error Detection (CED) based reliable XOR-XNOR circuit implementation to detect permanent and transient faults in ALUs during normal operation in order to improve the reliability of highly critical computer systems. The proposed design is performed using the 32 nm process technology.
KW - Concurrent error detection
KW - Fault model
KW - Fault-secure property
KW - Self-testing property
KW - XOR-XNOR circuits
UR - http://www.scopus.com/inward/record.url?scp=84871602946&partnerID=8YFLogxK
U2 - 10.1007/978-3-642-35606-3_61
DO - 10.1007/978-3-642-35606-3_61
M3 - Conference Proceeding
AN - SCOPUS:84871602946
SN - 9783642356056
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 516
EP - 523
BT - Network and Parallel Computing - 9th IFIP International Conference, NPC 2012, Proceedings
T2 - 9th IFIP International Conference on Network and Parallel Computing, NPC 2012
Y2 - 6 September 2012 through 8 September 2012
ER -