@inproceedings{7e7730c03cc945e291516dec8e7e4024,
title = "Concurrent error detection adder based on two paths output computation",
abstract = "This paper presents a concurrent error detection (CED) technique for a bit-slice of a full-adder. The proposed method involves computing the sum and carry bits in two alternative ways so that transient faults will be detected by comparing the results (Sum and Carry out) obtained from the two computing paths. This technique attempts to reduce the amount of extra hardware and cost of the circuit. In order to avoid the problem of extra time we will propagate the result when the first computation is finished so that dependent computation can commence execution as soon as possible. To prove the efficiency of the proposed method, the circuit is simulated in standard CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. The proposed design involves 12.12% saving in transistor count compared to DMR (Dual Modular Redundancy) style design.",
keywords = "Adder, Concurrent error detection, Duplicate computation, Transient fault",
author = "Chiraz Khedhiri and Mouna Karmani and Belgacem Hamdi and Man, {Ka Lok}",
year = "2011",
doi = "10.1109/ISPAW.2011.63",
language = "English",
isbn = "9780769544298",
series = "Proceedings - 9th IEEE International Symposium on Parallel and Distributed Processing with Applications Workshops, ISPAW 2011 - ICASE 2011, SGH 2011, GSDP 2011",
pages = "27--32",
booktitle = "Proceedings - 9th IEEE International Symposium on Parallel and Distributed Processing with Applications Workshops, ISPAW 2011 - ICASE 2011, SGH 2011, GSDP 2011",
note = "9th IEEE International Symposium on Parallel and Distributed Processing with Applications Workshops, ISPAW 2011 - 2011, ICASE 2011, SGH 2011, GSDP 2011 ; Conference date: 26-05-2011 Through 28-05-2011",
}