TY - JOUR
T1 - Composite field GF(((22)2)2) Advanced Encryption Standard (AES) S-box with algebraic normal form representation in the subfield inversion
AU - Wong, M. M.
AU - Wong, M. L.D.
AU - Nandi, A. K.
AU - Hijazin, I.
PY - 2011/11
Y1 - 2011/11
N2 - In this study, the authors categorise all of the feasible constructions for the composite Galois field GF(((22)2)2) Advanced Encryption Standard (AES) S-box into four main architectures by their field representations and their algebraic properties. For each of the categories, a new optimisation scheme which exploits algebraic normal form representation followed by a sub-structure sharing optimisation is presented. This is performed by converting the subfield GF((22) inversion into several logical expressions, which will be in turn reduced using a common sub-expression elimination algorithm. The authors show that this technique can effectively reduce the total area gate count as well as the critical path gate count in composite field AES S-boxes. The resulting architecture that achieves maximum reduction in both total area coverage and critical path gate count is found and reported. The hardware implementations of the authors proposed AES S-boxes, along with their performance and cost are presented and discussed.
AB - In this study, the authors categorise all of the feasible constructions for the composite Galois field GF(((22)2)2) Advanced Encryption Standard (AES) S-box into four main architectures by their field representations and their algebraic properties. For each of the categories, a new optimisation scheme which exploits algebraic normal form representation followed by a sub-structure sharing optimisation is presented. This is performed by converting the subfield GF((22) inversion into several logical expressions, which will be in turn reduced using a common sub-expression elimination algorithm. The authors show that this technique can effectively reduce the total area gate count as well as the critical path gate count in composite field AES S-boxes. The resulting architecture that achieves maximum reduction in both total area coverage and critical path gate count is found and reported. The hardware implementations of the authors proposed AES S-boxes, along with their performance and cost are presented and discussed.
UR - http://www.scopus.com/inward/record.url?scp=82855162247&partnerID=8YFLogxK
U2 - 10.1049/iet-cds.2010.0435
DO - 10.1049/iet-cds.2010.0435
M3 - Article
AN - SCOPUS:82855162247
SN - 1751-858X
VL - 5
SP - 471
EP - 476
JO - IET Circuits, Devices and Systems
JF - IET Circuits, Devices and Systems
IS - 6
ER -