Characterization and modeling of waffle MOSFETs for high frequency applications

Wen Wu; Sang Lam; Ping K. Ko; Mansun Chan

Characterization and modeling of waffle MOSFETs for high frequency applications

Wen Wu^*, Sang Lam, Ping K. Ko, Mansun Chan

^*Corresponding author for this work

Hong Kong University of Science and Technology

Research output: Contribution to conference › Paper › peer-review

Abstract

The high frequency characteristics of waffle MOSFETs are studied. In addition to area saving and reduction of junction capacitance, enhancement on RF characteristics and extra flexibility in the design window are also provided by waffle MOSFETs. The waffle layout has been applied to MOSFETs fabricated using a 0.35-μm CMOS bulk technology and compared with those designed with conventional multi-finger layouts. The waffle MOSFET offers about 50% reduction in the gate resistance. 30%-50% enhancement in f_max and 15% improvement on linearity (IIP3). With the validity of small-signal model demonstrated by the good matching between the model prediction and the measured S-parameter data, it indicates that the waffle MOSFET is capable of offering RF performance improvement with careful design.

Original language	English
Pages	163-166
Number of pages	4
Publication status	Published - 2004
Externally published	Yes
Event	2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 - Beijing, China Duration: 18 Oct 2004 → 21 Oct 2004

Conference

Conference	2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004
Country/Territory	China
City	Beijing
Period	18/10/04 → 21/10/04

Cite this

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title = "Characterization and modeling of waffle MOSFETs for high frequency applications",

abstract = "The high frequency characteristics of waffle MOSFETs are studied. In addition to area saving and reduction of junction capacitance, enhancement on RF characteristics and extra flexibility in the design window are also provided by waffle MOSFETs. The waffle layout has been applied to MOSFETs fabricated using a 0.35-μm CMOS bulk technology and compared with those designed with conventional multi-finger layouts. The waffle MOSFET offers about 50% reduction in the gate resistance. 30%-50% enhancement in fmax and 15% improvement on linearity (IIP3). With the validity of small-signal model demonstrated by the good matching between the model prediction and the measured S-parameter data, it indicates that the waffle MOSFET is capable of offering RF performance improvement with careful design.",

author = "Wen Wu and Sang Lam and Ko, {Ping K.} and Mansun Chan",

year = "2004",

language = "English",

pages = "163--166",

note = "2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 ; Conference date: 18-10-2004 Through 21-10-2004",

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TY - CONF

T1 - Characterization and modeling of waffle MOSFETs for high frequency applications

AU - Wu, Wen

AU - Lam, Sang

AU - Ko, Ping K.

AU - Chan, Mansun

PY - 2004

Y1 - 2004

N2 - The high frequency characteristics of waffle MOSFETs are studied. In addition to area saving and reduction of junction capacitance, enhancement on RF characteristics and extra flexibility in the design window are also provided by waffle MOSFETs. The waffle layout has been applied to MOSFETs fabricated using a 0.35-μm CMOS bulk technology and compared with those designed with conventional multi-finger layouts. The waffle MOSFET offers about 50% reduction in the gate resistance. 30%-50% enhancement in fmax and 15% improvement on linearity (IIP3). With the validity of small-signal model demonstrated by the good matching between the model prediction and the measured S-parameter data, it indicates that the waffle MOSFET is capable of offering RF performance improvement with careful design.

AB - The high frequency characteristics of waffle MOSFETs are studied. In addition to area saving and reduction of junction capacitance, enhancement on RF characteristics and extra flexibility in the design window are also provided by waffle MOSFETs. The waffle layout has been applied to MOSFETs fabricated using a 0.35-μm CMOS bulk technology and compared with those designed with conventional multi-finger layouts. The waffle MOSFET offers about 50% reduction in the gate resistance. 30%-50% enhancement in fmax and 15% improvement on linearity (IIP3). With the validity of small-signal model demonstrated by the good matching between the model prediction and the measured S-parameter data, it indicates that the waffle MOSFET is capable of offering RF performance improvement with careful design.

UR - http://www.scopus.com/inward/record.url?scp=21644452161&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:21644452161

SP - 163

EP - 166

T2 - 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004

Y2 - 18 October 2004 through 21 October 2004

ER -

Characterization and modeling of waffle MOSFETs for high frequency applications

Abstract

Conference

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