An extended HDL SoC TAB-model for diagnosability and repair

Vladimir Hahanov, Ka Lok Man, Baghdadi Ammar Awni Abbas, Eugenia Litvinova, Svetlana Chumachenko, Eng Gee Lim, Mark Leach

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

1 Citation (Scopus)

Abstract

This article describes technology for diagnosis SoC HDL-models, based on transaction graph. Methods for diagnosis is focused on decreasing the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. The following problems are solved: creation of digital system model in the form of transaction graph and multi-tree of fault detection tables, as well as ternary matrices for activating functional components of the selected set of monitors by using test patterns; development of a method for analyzing the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis.

Original languageEnglish
Title of host publicationIMECS 2015 - International MultiConference of Engineers and Computer Scientists 2015
EditorsS. I. Ao, Oscar Castillo, Craig Douglas, S. I. Ao, Craig Douglas, David Dagan Feng, Jeong-A Lee, S. I. Ao
PublisherNewswood Limited
Pages729-732
Number of pages4
ISBN (Electronic)9789881925398
Publication statusPublished - 2015
EventInternational MultiConference of Engineers and Computer Scientists 2015, IMECS 2015 - Tsimshatsui, Kowloon, Hong Kong
Duration: 18 Mar 201520 Mar 2015

Publication series

NameLecture Notes in Engineering and Computer Science
Volume2
ISSN (Print)2078-0958

Conference

ConferenceInternational MultiConference of Engineers and Computer Scientists 2015, IMECS 2015
Country/TerritoryHong Kong
CityTsimshatsui, Kowloon
Period18/03/1520/03/15

Keywords

  • Diagnosis
  • Faulty blocks detection
  • Hdl SoC model
  • Transaction graph

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