An efficient differential full adder

Chiraz Khedhiri; Mouna Karmani; Belgacem Hamdi; Ka Lok Man

doi:10.1142/9789814439084_0007

An efficient differential full adder

Chiraz Khedhiri, Mouna Karmani, Belgacem Hamdi, Ka Lok Man

Research output: Chapter in Book or Report/Conference proceeding › Chapter › peer-review

Abstract

In this chapter, an efficient differential full adder is presented. The circuit is simulated in double pass transistor CMOS at 32nm technology. This fully differential adder contains only 20 transistors which mean that we save 66.66% of the transistors number overhead if we compare the proposed design to the duplication based adder.

Original language	English
Title of host publication	IAENG Transactions on Electrical Engineering Volume 1
Subtitle of host publication	Special Issue of the International Multiconference of Engineers and Computer Scientists 2012
Publisher	World Scientific Publishing Co.
Pages	84-97
Number of pages	14
ISBN (Electronic)	9789814439084
ISBN (Print)	9789814439077
DOIs	https://doi.org/10.1142/9789814439084_0007
Publication status	Published - 1 Jan 2012
Externally published	Yes

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10.1142/9789814439084_0007

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An efficient differential full adder. / Khedhiri, Chiraz; Karmani, Mouna; Hamdi, Belgacem et al.
IAENG Transactions on Electrical Engineering Volume 1: Special Issue of the International Multiconference of Engineers and Computer Scientists 2012. World Scientific Publishing Co., 2012. p. 84-97.

Research output: Chapter in Book or Report/Conference proceeding › Chapter › peer-review

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An efficient differential full adder

Abstract

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