TY - GEN
T1 - Accurate constraints aware mapping on Coarse-Grained Reconfigurable Architecture
AU - Zhang, Peng
AU - Luo, Huiqiong
AU - Man, K. L.
PY - 2011
Y1 - 2011
N2 - The rapid diversification and evolution of wireless and multimedia standards change the flexibility of embedded processors from an option to the must. Coarse-Grained Reconfigurable Architectures (CGRAs) which make a good trade off between low power, non-programmable ASICs and high power, flexible DSPs become more and more popular. The mapping of the applications to CGRAs is the key to get high computational throughput. Because there is huge design space to explore on CGRAs, compilers must not only map the programs with high effectiveness, but also with high efficiency. However, there are many sorts of constraints exist during the mapping. Over or under estimate those constraints will lead to either low schedule quality or low efficiency. To meet this challenge, we propose an accurate constraints aware modulo scheduling approach: based on the co-analysis of the architecture and application, the compiler starts the scheduling with enough critical resources reserved and strictly make the retry follow the correct order. The experiments on wireless baseband programs show that the compilation can be speeded up by 300%.
AB - The rapid diversification and evolution of wireless and multimedia standards change the flexibility of embedded processors from an option to the must. Coarse-Grained Reconfigurable Architectures (CGRAs) which make a good trade off between low power, non-programmable ASICs and high power, flexible DSPs become more and more popular. The mapping of the applications to CGRAs is the key to get high computational throughput. Because there is huge design space to explore on CGRAs, compilers must not only map the programs with high effectiveness, but also with high efficiency. However, there are many sorts of constraints exist during the mapping. Over or under estimate those constraints will lead to either low schedule quality or low efficiency. To meet this challenge, we propose an accurate constraints aware modulo scheduling approach: based on the co-analysis of the architecture and application, the compiler starts the scheduling with enough critical resources reserved and strictly make the retry follow the correct order. The experiments on wireless baseband programs show that the compilation can be speeded up by 300%.
KW - Coarse-grain reconfigurable architectures
KW - Critical resource usage
KW - II search order
KW - Modulo scheduling
UR - http://www.scopus.com/inward/record.url?scp=80051955327&partnerID=8YFLogxK
U2 - 10.1109/ISPAW.2011.24
DO - 10.1109/ISPAW.2011.24
M3 - Conference Proceeding
AN - SCOPUS:80051955327
SN - 9780769544298
T3 - Proceedings - 9th IEEE International Symposium on Parallel and Distributed Processing with Applications Workshops, ISPAW 2011 - ICASE 2011, SGH 2011, GSDP 2011
SP - 39
EP - 44
BT - Proceedings - 9th IEEE International Symposium on Parallel and Distributed Processing with Applications Workshops, ISPAW 2011 - ICASE 2011, SGH 2011, GSDP 2011
T2 - 9th IEEE International Symposium on Parallel and Distributed Processing with Applications Workshops, ISPAW 2011 - 2011, ICASE 2011, SGH 2011, GSDP 2011
Y2 - 26 May 2011 through 28 May 2011
ER -