TY - GEN
T1 - A Survey on Hardware Prefetching in Shared-Memory Multiprocessors
AU - Adam, Shuaibu Musa
AU - Musa, Usman Ibrahim
AU - Siddique, Kamran
AU - Zhang, Jie
AU - Wang, Jingchen
AU - Hughes, Danny
AU - Man, Ka Lok
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Memory latency presents a significant obstruction to computer performance. To hide the memory latency, prefetching mechanism is used to retrieve data from the memory before the processor requests it, anticipating near-term data demands. An effective prefetching scheme can reduce cache miss rates and hide memory latency. Prefetching has yielded major advances in both industry and academia; modern high-performance processors nearly universally implement hardware prefetchers. In this paper, we introduce the fundamental concepts underpinning hardware prefetching and survey state-of-the-art hardware prefetching schemes. We delineate common prefetching approaches, analyse their relative merits and limitations, identify key challenges and open research questions. Overall, this paper aims to provide a comprehensive overview of hardware prefetching that highlights critical trends and technologies in this crucial performance optimisation domain.
AB - Memory latency presents a significant obstruction to computer performance. To hide the memory latency, prefetching mechanism is used to retrieve data from the memory before the processor requests it, anticipating near-term data demands. An effective prefetching scheme can reduce cache miss rates and hide memory latency. Prefetching has yielded major advances in both industry and academia; modern high-performance processors nearly universally implement hardware prefetchers. In this paper, we introduce the fundamental concepts underpinning hardware prefetching and survey state-of-the-art hardware prefetching schemes. We delineate common prefetching approaches, analyse their relative merits and limitations, identify key challenges and open research questions. Overall, this paper aims to provide a comprehensive overview of hardware prefetching that highlights critical trends and technologies in this crucial performance optimisation domain.
KW - computer performance
KW - hardware prefetching
KW - memory latency
KW - prefetching scheme
UR - http://www.scopus.com/inward/record.url?scp=85178032966&partnerID=8YFLogxK
U2 - 10.1109/EWDTS59469.2023.10297025
DO - 10.1109/EWDTS59469.2023.10297025
M3 - Conference Proceeding
AN - SCOPUS:85178032966
T3 - 2023 IEEE East-West Design and Test Symposium, EWDTS 2023 - Proceedings
BT - 2023 IEEE East-West Design and Test Symposium, EWDTS 2023 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE East-West Design and Test Symposium, EWDTS 2023
Y2 - 22 September 2023 through 25 September 2023
ER -