A self-test and self-repair approach for analog integrated circuits

Mouna Karmani*, Chiraz Khedhiri, Ka Lok Man, Tomas Krilavičius, Belgacem Hamdi, Amir Mohammad Rahmani

*Corresponding author for this work

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

Abstract

With the continuous increase of integration densities and complexities, secure integrated circuits (ICs) are more and more required to guarantee reliability for safety-critical applications in the presence of soft and hard faults. Thus, testing has become a real challenge for enhancing the reliability of safety-critical systems. This paper presents a Self-Test and Self-Repair approach which can be used to tolerate the most likely defects of bridging type that create a resistive path between VDD supply voltage and the ground occurring in analog CMOS circuits during the manufacturing process. The proposed testing approach is designed using the 65 nm CMOS technology. We then used an operational amplifier (OPA) to validate the technique and correlate it with post layout simulation results.

Original languageEnglish
Title of host publication2012 2nd Baltic Congress on Future Internet Communications, BCFIC 2012
Pages117-120
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 2nd Baltic Congress on Future Internet Communications, BCFIC 2012 - Vilnius, Lithuania
Duration: 25 Apr 201227 Apr 2012

Publication series

Name2012 2nd Baltic Congress on Future Internet Communications, BCFIC 2012

Conference

Conference2012 2nd Baltic Congress on Future Internet Communications, BCFIC 2012
Country/TerritoryLithuania
CityVilnius
Period25/04/1227/04/12

Keywords

  • 65 nm CMOS technology
  • Analog ICs
  • Bridging faults
  • Built-In Current Sensor (BICS)
  • Self-repair
  • Self-test

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