@inproceedings{75d3244e33084c5c88a7d0963f8b3a1a,
title = "A self-checking CMOS full adder in double pass transistor logic",
abstract = "This paper presents a self-checking implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS at 32nm technology and some transient faults are voluntarily injected in the layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to the implementation using standard CMOS technology.",
keywords = "Double pass transistor technology, Faults, Full adder, Self-checking",
author = "Chiraz Khedhiri and Mouna Karmani and Belgacem Hamdi and Man, {Ka Lok} and Yue Yang and Lixin Cheng",
year = "2012",
language = "English",
isbn = "9789881925190",
series = "Lecture Notes in Engineering and Computer Science",
publisher = "Newswood Limited",
pages = "1169--1172",
booktitle = "International MultiConference of Engineers and Computer Scientists, IMECS 2012",
note = "2012 International MultiConference of Engineers and Computer Scientists, IMECS 2012 ; Conference date: 14-03-2012 Through 16-03-2012",
}