A self-checking CMOS full adder in double pass transistor logic

Chiraz Khedhiri*, Mouna Karmani, Belgacem Hamdi, Ka Lok Man, Yue Yang, Lixin Cheng

*Corresponding author for this work

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

3 Citations (Scopus)

Abstract

This paper presents a self-checking implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS at 32nm technology and some transient faults are voluntarily injected in the layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to the implementation using standard CMOS technology.

Original languageEnglish
Title of host publicationInternational MultiConference of Engineers and Computer Scientists, IMECS 2012
PublisherNewswood Limited
Pages1169-1172
Number of pages4
ISBN (Print)9789881925190
Publication statusPublished - 2012
Event2012 International MultiConference of Engineers and Computer Scientists, IMECS 2012 - Kowloon, Hong Kong
Duration: 14 Mar 201216 Mar 2012

Publication series

NameLecture Notes in Engineering and Computer Science
Volume2196
ISSN (Print)2078-0958

Conference

Conference2012 International MultiConference of Engineers and Computer Scientists, IMECS 2012
Country/TerritoryHong Kong
CityKowloon
Period14/03/1216/03/12

Keywords

  • Double pass transistor technology
  • Faults
  • Full adder
  • Self-checking

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