A self-checking CMOS full adder in double pass transistor logic

Chiraz Khedhiri; Mouna Karmani; Belgacem Hamdi; Ka Lok Man; Yue Yang; Lixin Cheng

A self-checking CMOS full adder in double pass transistor logic

Chiraz Khedhiri^*, Mouna Karmani, Belgacem Hamdi, Ka Lok Man, Yue Yang, Lixin Cheng

^*Corresponding author for this work

Department of Computing

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

3 Citations (Scopus)

Abstract

This paper presents a self-checking implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS at 32nm technology and some transient faults are voluntarily injected in the layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to the implementation using standard CMOS technology.

Original language	English
Title of host publication	International MultiConference of Engineers and Computer Scientists, IMECS 2012
Publisher	Newswood Limited
Pages	1169-1172
Number of pages	4
ISBN (Print)	9789881925190
Publication status	Published - 2012
Event	2012 International MultiConference of Engineers and Computer Scientists, IMECS 2012 - Kowloon, Hong Kong Duration: 14 Mar 2012 → 16 Mar 2012

Publication series

Name	Lecture Notes in Engineering and Computer Science
Volume	2196
ISSN (Print)	2078-0958

Conference

Conference	2012 International MultiConference of Engineers and Computer Scientists, IMECS 2012
Country/Territory	Hong Kong
City	Kowloon
Period	14/03/12 → 16/03/12

Keywords

Double pass transistor technology
Faults
Full adder
Self-checking

Cite this

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title = "A self-checking CMOS full adder in double pass transistor logic",

abstract = "This paper presents a self-checking implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS at 32nm technology and some transient faults are voluntarily injected in the layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to the implementation using standard CMOS technology.",

keywords = "Double pass transistor technology, Faults, Full adder, Self-checking",

author = "Chiraz Khedhiri and Mouna Karmani and Belgacem Hamdi and Man, {Ka Lok} and Yue Yang and Lixin Cheng",

year = "2012",

language = "English",

isbn = "9789881925190",

series = "Lecture Notes in Engineering and Computer Science",

publisher = "Newswood Limited",

pages = "1169--1172",

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Khedhiri, C, Karmani, M, Hamdi, B, Man, KL, Yang, Y & Cheng, L 2012, A self-checking CMOS full adder in double pass transistor logic. in International MultiConference of Engineers and Computer Scientists, IMECS 2012. Lecture Notes in Engineering and Computer Science, vol. 2196, Newswood Limited, pp. 1169-1172, 2012 International MultiConference of Engineers and Computer Scientists, IMECS 2012, Kowloon, Hong Kong, 14/03/12.

A self-checking CMOS full adder in double pass transistor logic. / Khedhiri, Chiraz; Karmani, Mouna; Hamdi, Belgacem et al.
International MultiConference of Engineers and Computer Scientists, IMECS 2012. Newswood Limited, 2012. p. 1169-1172 (Lecture Notes in Engineering and Computer Science; Vol. 2196).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

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AU - Karmani, Mouna

AU - Hamdi, Belgacem

AU - Man, Ka Lok

AU - Yang, Yue

AU - Cheng, Lixin

PY - 2012

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AB - This paper presents a self-checking implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS at 32nm technology and some transient faults are voluntarily injected in the layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to the implementation using standard CMOS technology.

KW - Double pass transistor technology

KW - Faults

KW - Full adder

KW - Self-checking

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A self-checking CMOS full adder in double pass transistor logic

Abstract

Publication series

Conference

Keywords

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Cite this