TY - JOUR
T1 - A Reconfigurable and Pipelined Architecture for Standard-Compatible LDPC and Polar Decoding
AU - Cao, Shan
AU - Lin, Ting
AU - Zhang, Shunqing
AU - Xu, Shugong
AU - Zhang, Chuan
N1 - Publisher Copyright:
© 1967-2012 IEEE.
PY - 2021/6
Y1 - 2021/6
N2 - With low-density parity-check (LDPC) codes and polar codes selected as the standard codes for the fifth generation (5 G) enhanced Mobile Broad Band scenario (eMBB), a decoding architecture that can simultaneously support the decoding of control and data plane becomes necessary at the terminal side to meet the raising requirement for 5 G network deployment. Due to the special structure of LDPC codes according to the Release 15 (R15) 5 G standard, a straight-forward extension of the existing reconfigurable scheme is in general difficult. Therefore in this paper, a unified decoding architecture is proposed that can be reconfigured to either LDPC codes or polar codes. Due to various differences between the two codes such as parity-check matrices, codeword lengths and iterative methods, a joint decoding algorithm is introduced by reordering basic decoding operations to the unified add-comparison-add pattern for both codes. Then, a pipelined structure of reconfigurable decoding unit (RDU) is presented correspondingly which is fully compatible with all decoding patterns of the R15 standard. And finally, a reconfigurable decoder is proposed with multiple levels of parallelism, and the reconfiguration scheme is introduced to improve the hardware utilization and decoding efficiency. The proposed decoder is implemented in FPGA and ASIC, respectively, and has achieved state-of-the-art performance in throughput and area efficiency compared to LDPC-only and polar-only decoders.
AB - With low-density parity-check (LDPC) codes and polar codes selected as the standard codes for the fifth generation (5 G) enhanced Mobile Broad Band scenario (eMBB), a decoding architecture that can simultaneously support the decoding of control and data plane becomes necessary at the terminal side to meet the raising requirement for 5 G network deployment. Due to the special structure of LDPC codes according to the Release 15 (R15) 5 G standard, a straight-forward extension of the existing reconfigurable scheme is in general difficult. Therefore in this paper, a unified decoding architecture is proposed that can be reconfigured to either LDPC codes or polar codes. Due to various differences between the two codes such as parity-check matrices, codeword lengths and iterative methods, a joint decoding algorithm is introduced by reordering basic decoding operations to the unified add-comparison-add pattern for both codes. Then, a pipelined structure of reconfigurable decoding unit (RDU) is presented correspondingly which is fully compatible with all decoding patterns of the R15 standard. And finally, a reconfigurable decoder is proposed with multiple levels of parallelism, and the reconfiguration scheme is introduced to improve the hardware utilization and decoding efficiency. The proposed decoder is implemented in FPGA and ASIC, respectively, and has achieved state-of-the-art performance in throughput and area efficiency compared to LDPC-only and polar-only decoders.
KW - decoder
KW - LDPC code
KW - polar code
KW - reconfigurable architecture
KW - standard-compatible
UR - http://www.scopus.com/inward/record.url?scp=85104634613&partnerID=8YFLogxK
U2 - 10.1109/TVT.2021.3075232
DO - 10.1109/TVT.2021.3075232
M3 - Article
AN - SCOPUS:85104634613
SN - 0018-9545
VL - 70
SP - 5431
EP - 5444
JO - IEEE Transactions on Vehicular Technology
JF - IEEE Transactions on Vehicular Technology
IS - 6
M1 - 9415136
ER -