TY - GEN
T1 - A Flexible Framework Based on Finite-Element Method for Capacitance Extraction of 3-Dimensional Interconnects
AU - Zheng, Qiwen
AU - Wu, Ye
AU - Zhang, Zichang
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This paper proposed a capacitance extraction framework based on finite-element methods (FEM) to obtain the capacitance of three-dimensional (3-D) interconnect structures with multi-layer dielectrics. The proposed framework is demonstrated through its application to various 3-D interconnect configurations, revealing an error of no more than 8.03 % when compared to the commercial software Q3D, and 3.44 % compared to published papers. Notably, this framework exhibits enhanced flexibility in modeling and meshing, leading to a 1.5 % decrease in CPU time and a 40.7 % reduction in memory consumption compared to Q3D by optimizing the meshing strategy. Meanwhile, the proposed approach is based on the open-source software Gmsh and GetDP, ensuring high portability. Consequently, it can be adapted to various 3D interconnect structures, offering significant potential in designing very large-scale integrated circuits (VLSI) and enabling highly accurate parasitic extraction in post-layout simulations.
AB - This paper proposed a capacitance extraction framework based on finite-element methods (FEM) to obtain the capacitance of three-dimensional (3-D) interconnect structures with multi-layer dielectrics. The proposed framework is demonstrated through its application to various 3-D interconnect configurations, revealing an error of no more than 8.03 % when compared to the commercial software Q3D, and 3.44 % compared to published papers. Notably, this framework exhibits enhanced flexibility in modeling and meshing, leading to a 1.5 % decrease in CPU time and a 40.7 % reduction in memory consumption compared to Q3D by optimizing the meshing strategy. Meanwhile, the proposed approach is based on the open-source software Gmsh and GetDP, ensuring high portability. Consequently, it can be adapted to various 3D interconnect structures, offering significant potential in designing very large-scale integrated circuits (VLSI) and enabling highly accurate parasitic extraction in post-layout simulations.
KW - 3-D interconnects
KW - capacitance extraction
KW - finite-element methods (FEM)
KW - GetDP
KW - Gmsh
UR - http://www.scopus.com/inward/record.url?scp=85206468122&partnerID=8YFLogxK
U2 - 10.1109/ICSE62991.2024.10681369
DO - 10.1109/ICSE62991.2024.10681369
M3 - Conference Proceeding
AN - SCOPUS:85206468122
T3 - IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
SP - 144
EP - 147
BT - 2024 16th IEEE International Conference on Semiconductor Electronics, ICSE 2024 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th IEEE International Conference on Semiconductor Electronics, ICSE 2024
Y2 - 19 August 2024 through 21 August 2024
ER -