TY - GEN
T1 - A Computational-Efficient Deformable Convolution Network Accelerator via Hardware and Algorithm Co-Optimization
AU - Li, Shan
AU - Cao, Shan
AU - Hui, Lanqing
AU - Jiang, Zhiyuan
AU - Sun, Yanzan
AU - Xu, Shugong
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Deformable convolution networks (DCNs) shows performance boosts on object recognition tasks by enabling variable geometric modeling. However, the irregular addressing of memory accesses makes it inefficient for hardware acceleration. In this paper, we propose a computational-efficient hardware accelerator for DCNs. First, a hardware-friendly DCNs inference scheme is introduced based on the original DCNs algorithm with little accuracy loss. Secondly, a hardware accelerator architecture is presented correspondingly, and an speed matching method is introduced to maximizing the number of deformable layers without latency increase. The proposed accelerator is implemented on the Arria 10 FPGA, results of which show that the proposed design achieves the highest throughput and DSP efficiency compared with state-of-the-art DCNs accelerators.
AB - Deformable convolution networks (DCNs) shows performance boosts on object recognition tasks by enabling variable geometric modeling. However, the irregular addressing of memory accesses makes it inefficient for hardware acceleration. In this paper, we propose a computational-efficient hardware accelerator for DCNs. First, a hardware-friendly DCNs inference scheme is introduced based on the original DCNs algorithm with little accuracy loss. Secondly, a hardware accelerator architecture is presented correspondingly, and an speed matching method is introduced to maximizing the number of deformable layers without latency increase. The proposed accelerator is implemented on the Arria 10 FPGA, results of which show that the proposed design achieves the highest throughput and DSP efficiency compared with state-of-the-art DCNs accelerators.
KW - deformable convolution
KW - FPGA
KW - Hardware accelerator
KW - hardware-friendly algorithm
UR - http://www.scopus.com/inward/record.url?scp=85141763307&partnerID=8YFLogxK
U2 - 10.1109/SiPS55645.2022.9919242
DO - 10.1109/SiPS55645.2022.9919242
M3 - Conference Proceeding
AN - SCOPUS:85141763307
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
BT - 2022 IEEE Workshop on Signal Processing Systems, SiPS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 36th IEEE Workshop on Signal Processing Systems, SiPS 2022
Y2 - 2 November 2022 through 4 November 2022
ER -