A 2.5 ppm/°C voltage reference combining traditional bgr and ztc mosfet high-order curvature compensation

Xifeng Liu; Shan Liang; Wenju Liu; Ping Sun

doi:10.1109/TCSII.2020.3027768

A 2.5 ppm/°C voltage reference combining traditional bgr and ztc mosfet high-order curvature compensation

Xifeng Liu^*, Shan Liang, Wenju Liu, Ping Sun

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

11 Citations (Scopus)

Abstract

This brief presents a voltage reference with high-order curvature compensation based on the zero temperature coefficient (ZTC) of MOSFET. The proposed voltage reference uses a conventional current reference to generate a constant current as of the bias of ZTCMOS. A curvature compensation method based on the α power model is combined with the conventional curvature compensation method to obtain a low temperature coefficient. Test results of the proposed voltage reference fabricated with the CSMC 0.18μ m CMOS process demonstrate that the output voltage is 628mV. The trimmed temperature coefficient achieves 2.5 ppm/°C. The line sensitivity is 0.03 %/V, the chip area is 0.024 mm2, power consumption is 77 μ W. The simulated power supply rejection ratio (PSRR) reaches -91.4 dB at 100 MHz.

Original language	English
Article number	9209100
Pages (from-to)	1093-1097
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	68
Issue number	4
DOIs	https://doi.org/10.1109/TCSII.2020.3027768
Publication status	Published - Apr 2021
Externally published	Yes

Keywords

Cmos process
Curvature compensation
PSRR
Voltage reference
ZTC
α Power model

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10.1109/TCSII.2020.3027768

Cite this

@article{d02ab6bd0e654deba7183e6517974f24,

title = "A 2.5 ppm/°C voltage reference combining traditional bgr and ztc mosfet high-order curvature compensation",

abstract = "This brief presents a voltage reference with high-order curvature compensation based on the zero temperature coefficient (ZTC) of MOSFET. The proposed voltage reference uses a conventional current reference to generate a constant current as of the bias of ZTCMOS. A curvature compensation method based on the α power model is combined with the conventional curvature compensation method to obtain a low temperature coefficient. Test results of the proposed voltage reference fabricated with the CSMC 0.18μ m CMOS process demonstrate that the output voltage is 628mV. The trimmed temperature coefficient achieves 2.5 ppm/°C. The line sensitivity is 0.03 %/V, the chip area is 0.024 mm2, power consumption is 77 μ W. The simulated power supply rejection ratio (PSRR) reaches -91.4 dB at 100 MHz.",

keywords = "Cmos process, Curvature compensation, PSRR, Voltage reference, ZTC, α Power model",

author = "Xifeng Liu and Shan Liang and Wenju Liu and Ping Sun",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2021",

month = apr,

doi = "10.1109/TCSII.2020.3027768",

language = "English",

volume = "68",

pages = "1093--1097",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

number = "4",

}

TY - JOUR

T1 - A 2.5 ppm/°C voltage reference combining traditional bgr and ztc mosfet high-order curvature compensation

AU - Liu, Xifeng

AU - Liang, Shan

AU - Liu, Wenju

AU - Sun, Ping

PY - 2021/4

Y1 - 2021/4

N2 - This brief presents a voltage reference with high-order curvature compensation based on the zero temperature coefficient (ZTC) of MOSFET. The proposed voltage reference uses a conventional current reference to generate a constant current as of the bias of ZTCMOS. A curvature compensation method based on the α power model is combined with the conventional curvature compensation method to obtain a low temperature coefficient. Test results of the proposed voltage reference fabricated with the CSMC 0.18μ m CMOS process demonstrate that the output voltage is 628mV. The trimmed temperature coefficient achieves 2.5 ppm/°C. The line sensitivity is 0.03 %/V, the chip area is 0.024 mm2, power consumption is 77 μ W. The simulated power supply rejection ratio (PSRR) reaches -91.4 dB at 100 MHz.

AB - This brief presents a voltage reference with high-order curvature compensation based on the zero temperature coefficient (ZTC) of MOSFET. The proposed voltage reference uses a conventional current reference to generate a constant current as of the bias of ZTCMOS. A curvature compensation method based on the α power model is combined with the conventional curvature compensation method to obtain a low temperature coefficient. Test results of the proposed voltage reference fabricated with the CSMC 0.18μ m CMOS process demonstrate that the output voltage is 628mV. The trimmed temperature coefficient achieves 2.5 ppm/°C. The line sensitivity is 0.03 %/V, the chip area is 0.024 mm2, power consumption is 77 μ W. The simulated power supply rejection ratio (PSRR) reaches -91.4 dB at 100 MHz.

KW - Cmos process

KW - Curvature compensation

KW - PSRR

KW - Voltage reference

KW - ZTC

KW - α Power model

UR - http://www.scopus.com/inward/record.url?scp=85103455033&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2020.3027768

DO - 10.1109/TCSII.2020.3027768

M3 - Article

AN - SCOPUS:85103455033

SN - 1549-7747

VL - 68

SP - 1093

EP - 1097

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 4

M1 - 9209100

ER -

A 2.5 ppm/°C voltage reference combining traditional bgr and ztc mosfet high-order curvature compensation

Abstract

Keywords

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