The design of bus accessing timing to NAND flash array for high bandwidth

To improve the reading and writing speed of NAND flash array with multi-channel and multi-way, and to obtain the highest available bandwidth, an approach is presented in this paper. One mechanism of high efficiency bus accessing timing scheme based on interleaving is introduced into the approach. In pursuance of this timing, flash controllers are able to make every plane in the flash array to be active in parallel. Therefore the transmission ability to and from the bus can be greatly improved. Utilizing this approach, the accessing efficiency to the NAND flash array will be pushed to a very high level. According to the testing results, as opposed to normal flash bus timing scheme, the data reading efficiency can be increased by 68.5%, and the data writing efficiency can be increased by 457%, with the flash bus timing scheme presented in this paper being used. The conclusion can be drawn that the flash bus timing scheme presented in this paper is effective, and the reading and writing at very high speed to the NAND flash array can be realized.