TY - GEN
T1 - TAB-model for multilevel diagnosis and repair of HDL SoC
AU - Hahanov, Vladimir
AU - Man, Ka Lok
AU - Abbas, Baghdadi Ammar Awni
AU - Litvinova, Eugenia
AU - Chumachenko, Svetlana
AU - Ahn, Jihyeok
AU - Kim, Kyung Ki
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2015/4/16
Y1 - 2015/4/16
N2 - This paper describes technology for diagnosis SoC HDL-models, based on transaction graph. Diagnosis method is focused on decreasing the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. A method for analyzing the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis is given.
AB - This paper describes technology for diagnosis SoC HDL-models, based on transaction graph. Diagnosis method is focused on decreasing the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. A method for analyzing the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis is given.
KW - HDL SoC model
KW - diagnosis
KW - faulty blocks detection
KW - transaction graph
UR - http://www.scopus.com/inward/record.url?scp=84929323052&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2014.7087686
DO - 10.1109/ISOCC.2014.7087686
M3 - Conference Proceeding
AN - SCOPUS:84929323052
T3 - ISOCC 2014 - International SoC Design Conference
SP - 181
EP - 182
BT - ISOCC 2014 - International SoC Design Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th International SoC Design Conference, ISOCC 2014
Y2 - 3 November 2014 through 6 November 2014
ER -