TAB-model for multilevel diagnosis and repair of HDL SoC

Vladimir Hahanov, Ka Lok Man, Baghdadi Ammar Awni Abbas, Eugenia Litvinova, Svetlana Chumachenko, Jihyeok Ahn, Kyung Ki Kim

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

Abstract

This paper describes technology for diagnosis SoC HDL-models, based on transaction graph. Diagnosis method is focused on decreasing the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. A method for analyzing the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis is given.

Original languageEnglish
Title of host publicationISOCC 2014 - International SoC Design Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages181-182
Number of pages2
ISBN (Electronic)9781479951260
DOIs
Publication statusPublished - 16 Apr 2015
Event11th International SoC Design Conference, ISOCC 2014 - Jeju, Korea, Republic of
Duration: 3 Nov 20146 Nov 2014

Publication series

NameISOCC 2014 - International SoC Design Conference

Conference

Conference11th International SoC Design Conference, ISOCC 2014
Country/TerritoryKorea, Republic of
CityJeju
Period3/11/146/11/14

Keywords

  • HDL SoC model
  • diagnosis
  • faulty blocks detection
  • transaction graph

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