TAB-model for multilevel diagnosis and repair of HDL SoC

Vladimir Hahanov; Ka Lok Man; Baghdadi Ammar Awni Abbas; Eugenia Litvinova; Svetlana Chumachenko; Jihyeok Ahn; Kyung Ki Kim

doi:10.1109/ISOCC.2014.7087686

TAB-model for multilevel diagnosis and repair of HDL SoC

Vladimir Hahanov, Ka Lok Man, Baghdadi Ammar Awni Abbas, Eugenia Litvinova, Svetlana Chumachenko, Jihyeok Ahn, Kyung Ki Kim

Department of Computing

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

Abstract

This paper describes technology for diagnosis SoC HDL-models, based on transaction graph. Diagnosis method is focused on decreasing the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. A method for analyzing the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis is given.

Original language	English
Title of host publication	ISOCC 2014 - International SoC Design Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	181-182
Number of pages	2
ISBN (Electronic)	9781479951260
DOIs	https://doi.org/10.1109/ISOCC.2014.7087686
Publication status	Published - 16 Apr 2015
Event	11th International SoC Design Conference, ISOCC 2014 - Jeju, Korea, Republic of Duration: 3 Nov 2014 → 6 Nov 2014

Publication series

Name	ISOCC 2014 - International SoC Design Conference

Conference

Conference	11th International SoC Design Conference, ISOCC 2014
Country/Territory	Korea, Republic of
City	Jeju
Period	3/11/14 → 6/11/14

Keywords

HDL SoC model
diagnosis
faulty blocks detection
transaction graph

Access to Document

10.1109/ISOCC.2014.7087686

Cite this

Hahanov, V., Man, K. L., Abbas, B. A. A., Litvinova, E., Chumachenko, S., Ahn, J., & Kim, K. K. (2015). TAB-model for multilevel diagnosis and repair of HDL SoC. In ISOCC 2014 - International SoC Design Conference (pp. 181-182). Article 7087686 (ISOCC 2014 - International SoC Design Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2014.7087686

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title = "TAB-model for multilevel diagnosis and repair of HDL SoC",

abstract = "This paper describes technology for diagnosis SoC HDL-models, based on transaction graph. Diagnosis method is focused on decreasing the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. A method for analyzing the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis is given.",

keywords = "HDL SoC model, diagnosis, faulty blocks detection, transaction graph",

author = "Vladimir Hahanov and Man, {Ka Lok} and Abbas, {Baghdadi Ammar Awni} and Eugenia Litvinova and Svetlana Chumachenko and Jihyeok Ahn and Kim, {Kyung Ki}",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 11th International SoC Design Conference, ISOCC 2014 ; Conference date: 03-11-2014 Through 06-11-2014",

year = "2015",

month = apr,

day = "16",

doi = "10.1109/ISOCC.2014.7087686",

language = "English",

series = "ISOCC 2014 - International SoC Design Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Hahanov, V, Man, KL, Abbas, BAA, Litvinova, E, Chumachenko, S, Ahn, J & Kim, KK 2015, TAB-model for multilevel diagnosis and repair of HDL SoC. in ISOCC 2014 - International SoC Design Conference., 7087686, ISOCC 2014 - International SoC Design Conference, Institute of Electrical and Electronics Engineers Inc., pp. 181-182, 11th International SoC Design Conference, ISOCC 2014, Jeju, Korea, Republic of, 3/11/14. https://doi.org/10.1109/ISOCC.2014.7087686

TAB-model for multilevel diagnosis and repair of HDL SoC. / Hahanov, Vladimir; Man, Ka Lok; Abbas, Baghdadi Ammar Awni et al.
ISOCC 2014 - International SoC Design Conference. Institute of Electrical and Electronics Engineers Inc., 2015. p. 181-182 7087686 (ISOCC 2014 - International SoC Design Conference).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

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T1 - TAB-model for multilevel diagnosis and repair of HDL SoC

AU - Hahanov, Vladimir

AU - Man, Ka Lok

AU - Abbas, Baghdadi Ammar Awni

AU - Litvinova, Eugenia

AU - Chumachenko, Svetlana

AU - Ahn, Jihyeok

AU - Kim, Kyung Ki

PY - 2015/4/16

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N2 - This paper describes technology for diagnosis SoC HDL-models, based on transaction graph. Diagnosis method is focused on decreasing the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. A method for analyzing the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis is given.

AB - This paper describes technology for diagnosis SoC HDL-models, based on transaction graph. Diagnosis method is focused on decreasing the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. A method for analyzing the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis is given.

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PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 11th International SoC Design Conference, ISOCC 2014

Y2 - 3 November 2014 through 6 November 2014

ER -

TAB-model for multilevel diagnosis and repair of HDL SoC

Abstract

Publication series

Conference

Keywords

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