Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process

Chun Zhao*, W. Zhang, C. Z. Zhao, K. L. Man, T. T. Jeong, J. K. Seon, Y. Lee

*Corresponding author for this work

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

4 Citations (Scopus)

Abstract

The Application Specific Integrated Circuit (ASIC) design approach depends highly on the quality of the cell library to meet design specifications. Due to the use of both digital and analog signal processing, mixed-signal integrated circuits library are usually designed for specific purposes and the related design requires a high level of expertise and careful use of computer aided design tools. The paper establishes a series of standard cell: scan D flip-flops based on 0.5 micron complementary metal oxide semiconductor mixed-signal process. The research work presented in this paper includes reverse engineering, standard cell schematic and symbol building, standard cell layout drawing and post layout simulation.

Original languageEnglish
Title of host publication2011 International SoC Design Conference, ISOCC 2011
PublisherIEEE Computer Society
Pages306-309
Number of pages4
ISBN (Print)9781457707100
DOIs
Publication statusPublished - 2011
Event8th International SoC Design Conference 2011, ISOCC 2011 - Jeju, Korea, Republic of
Duration: 17 Nov 201118 Nov 2011

Publication series

Name2011 International SoC Design Conference, ISOCC 2011

Conference

Conference8th International SoC Design Conference 2011, ISOCC 2011
Country/TerritoryKorea, Republic of
CityJeju
Period17/11/1118/11/11

Keywords

  • IC design
  • Layout
  • Scan D flip-flops
  • Standard cell libray
  • Tanner EDA tools

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