Realization of compact MOSFET structure by waffle-layout

Sang Lam*, Wing Hung Ki, Ka Chun Kwok, Mansun Chan

*Corresponding author for this work

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

2 Citations (Scopus)


A compact wide MOSFET layout strategy using a waffle layout design is presented. The waffle-layout MOSFET"s have been fabricated using a 0.35-μm CMOS process. Experimental results show a higher transconductance (gm/W, gm/ID) of the devices at low current drive resulting a more than 10% improvement in transistor DC voltage gain. The design also gives considerable reduction in device area and 25% reduction in drain capacitance compared with the multifinger counterpart.

Original languageEnglish
Title of host publicationEuropean Solid-State Device Research Conference
EditorsHeiner Ryssel, Gerhard Wachutka, Herbert Grunbacher
PublisherIEEE Computer Society
Number of pages4
ISBN (Electronic)2914601018
Publication statusPublished - 2001
Externally publishedYes
Event31st European Solid-State Device Research Conference, ESSDERC 2001 - Nuremberg, Germany
Duration: 11 Sept 200113 Sept 2001

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876


Conference31st European Solid-State Device Research Conference, ESSDERC 2001

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