Realization of compact MOSFET structure by waffle-layout

Sang Lam; Wing Hung Ki; Ka Chun Kwok; Mansun Chan

doi:10.1109/ESSDERC.2001.195215

Realization of compact MOSFET structure by waffle-layout

Sang Lam^*, Wing Hung Ki, Ka Chun Kwok, Mansun Chan

^*Corresponding author for this work

Hong Kong University of Science and Technology

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

2 Citations (Scopus)

Abstract

A compact wide MOSFET layout strategy using a waffle layout design is presented. The waffle-layout MOSFET"s have been fabricated using a 0.35-μm CMOS process. Experimental results show a higher transconductance (g_m/W, g_m/I_D) of the devices at low current drive resulting a more than 10% improvement in transistor DC voltage gain. The design also gives considerable reduction in device area and 25% reduction in drain capacitance compared with the multifinger counterpart.

Original language	English
Title of host publication	European Solid-State Device Research Conference
Editors	Heiner Ryssel, Gerhard Wachutka, Herbert Grunbacher
Publisher	IEEE Computer Society
Pages	119-122
Number of pages	4
ISBN (Electronic)	2914601018
DOIs	https://doi.org/10.1109/ESSDERC.2001.195215
Publication status	Published - 2001
Externally published	Yes
Event	31st European Solid-State Device Research Conference, ESSDERC 2001 - Nuremberg, Germany Duration: 11 Sept 2001 → 13 Sept 2001

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Conference

Conference	31st European Solid-State Device Research Conference, ESSDERC 2001
Country/Territory	Germany
City	Nuremberg
Period	11/09/01 → 13/09/01

Access to Document

10.1109/ESSDERC.2001.195215

Cite this

@inproceedings{b140482c51e141a3a4b006c895e8c4e1,

title = "Realization of compact MOSFET structure by waffle-layout",

abstract = "A compact wide MOSFET layout strategy using a waffle layout design is presented. The waffle-layout MOSFET{"}s have been fabricated using a 0.35-μm CMOS process. Experimental results show a higher transconductance (gm/W, gm/ID) of the devices at low current drive resulting a more than 10% improvement in transistor DC voltage gain. The design also gives considerable reduction in device area and 25% reduction in drain capacitance compared with the multifinger counterpart.",

author = "Sang Lam and Ki, {Wing Hung} and Kwok, {Ka Chun} and Mansun Chan",

note = "Publisher Copyright: {\textcopyright} 2001 Non IEEE.; 31st European Solid-State Device Research Conference, ESSDERC 2001 ; Conference date: 11-09-2001 Through 13-09-2001",

year = "2001",

doi = "10.1109/ESSDERC.2001.195215",

language = "English",

series = "European Solid-State Device Research Conference",

publisher = "IEEE Computer Society",

pages = "119--122",

editor = "Heiner Ryssel and Gerhard Wachutka and Herbert Grunbacher",

booktitle = "European Solid-State Device Research Conference",

}

Lam, S, Ki, WH, Kwok, KC & Chan, M 2001, Realization of compact MOSFET structure by waffle-layout. in H Ryssel, G Wachutka & H Grunbacher (eds), European Solid-State Device Research Conference. European Solid-State Device Research Conference, IEEE Computer Society, pp. 119-122, 31st European Solid-State Device Research Conference, ESSDERC 2001, Nuremberg, Germany, 11/09/01. https://doi.org/10.1109/ESSDERC.2001.195215

Realization of compact MOSFET structure by waffle-layout. / Lam, Sang; Ki, Wing Hung; Kwok, Ka Chun et al.
European Solid-State Device Research Conference. ed. / Heiner Ryssel; Gerhard Wachutka; Herbert Grunbacher. IEEE Computer Society, 2001. p. 119-122 (European Solid-State Device Research Conference).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

TY - GEN

T1 - Realization of compact MOSFET structure by waffle-layout

AU - Lam, Sang

AU - Ki, Wing Hung

AU - Kwok, Ka Chun

AU - Chan, Mansun

PY - 2001

Y1 - 2001

N2 - A compact wide MOSFET layout strategy using a waffle layout design is presented. The waffle-layout MOSFET"s have been fabricated using a 0.35-μm CMOS process. Experimental results show a higher transconductance (gm/W, gm/ID) of the devices at low current drive resulting a more than 10% improvement in transistor DC voltage gain. The design also gives considerable reduction in device area and 25% reduction in drain capacitance compared with the multifinger counterpart.

AB - A compact wide MOSFET layout strategy using a waffle layout design is presented. The waffle-layout MOSFET"s have been fabricated using a 0.35-μm CMOS process. Experimental results show a higher transconductance (gm/W, gm/ID) of the devices at low current drive resulting a more than 10% improvement in transistor DC voltage gain. The design also gives considerable reduction in device area and 25% reduction in drain capacitance compared with the multifinger counterpart.

UR - http://www.scopus.com/inward/record.url?scp=84907483632&partnerID=8YFLogxK

U2 - 10.1109/ESSDERC.2001.195215

DO - 10.1109/ESSDERC.2001.195215

M3 - Conference Proceeding

AN - SCOPUS:84907483632

T3 - European Solid-State Device Research Conference

SP - 119

EP - 122

BT - European Solid-State Device Research Conference

A2 - Ryssel, Heiner

A2 - Wachutka, Gerhard

A2 - Grunbacher, Herbert

PB - IEEE Computer Society

T2 - 31st European Solid-State Device Research Conference, ESSDERC 2001

Y2 - 11 September 2001 through 13 September 2001

ER -

Realization of compact MOSFET structure by waffle-layout

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