Process algebraic specification of DI circuits

Ka Lok Man, Abhinav Asthana, Hemangee K. Kapoor, Tomas Krilavičius, Jian Chang

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

1 Citation (Scopus)

Abstract

The purpose of this paper is to investigate applicability of Null Conventional Logic (NCL) for synthesising asynchronous control circuits using. The target implementation being delay insensitive (DI), the specification language also should be DI. Delay Insensitive Sequential Processes (DISP) is such a process algebraic language where the behaviour of asynchronous control logic blocks can be expressed as processes. We have mapped several basic DISP constructs to NCL and performed a small cases study. It is a step towards an alternative synthesis way for NCL circuits.

Original languageEnglish
Title of host publication2010 International SoC Design Conference, ISOCC 2010
Pages396-399
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 International SoC Design Conference, ISOCC 2010 - Incheon, Korea, Republic of
Duration: 22 Nov 201023 Nov 2010

Publication series

Name2010 International SoC Design Conference, ISOCC 2010

Conference

Conference2010 International SoC Design Conference, ISOCC 2010
Country/TerritoryKorea, Republic of
CityIncheon
Period22/11/1023/11/10

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