Power reduction and technology mapping of digital circuits using AND-inverter graphs

R. Mehrotra*, E. Popovici, K. L. Man, M. Schellekens

*Corresponding author for this work

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

6 Citations (Scopus)

Abstract

The minimisation of power consumption is an important design goal for digital circuits. The switching activity of a CMOS digital circuit significantly contributes to overall power dissipation. By approximating the switching activity of circuit nodes as internal switching probabilities using AND Inverter Graphs (AIGs), it is possible to estimate the dynamic power dissipation characteristic of circuits. A technique for minimising the overall sum of switching probabilities is presented. The method is based on local reordering and swapping of nodes in AIG representing the functionality of the circuit to be realised. This paper also focuses on the problem of mapping a technology independent circuit to a specific technology, using specific gates and cells (AND cells, inverters and buffers) from a given library, with power as the optimisation metric. The resulting circuit that is obtained by mapping the AIG after switching probability optimisation has shown in simulation reduced power dissipation characteristic without an area penalty.

Original languageEnglish
Title of host publication2010 27th International Conference on Microelectronics, MIEL 2010 - Proceedings
Pages295-298
Number of pages4
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 27th International Conference on Microelectronics, MIEL 2010 - Nis, Serbia
Duration: 16 May 201019 May 2010

Publication series

Name2010 27th International Conference on Microelectronics, MIEL 2010 - Proceedings

Conference

Conference2010 27th International Conference on Microelectronics, MIEL 2010
Country/TerritorySerbia
CityNis
Period16/05/1019/05/10

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