Pipelined implementations of polar encoder and feed-back part for SC polar decoder

Chuan Zhang, Junmei Yang, Xiaohu You, Shugong Xu

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

32 Citations (Scopus)

Abstract

In this paper, we first reveal the similarity of polar encoder and fast Fourier transform (FFT) processor. Based on this, both feed-forward and feed-back pipelined implementations of polar encoder are proposed. It is pointed out that the feedback part of SC polar decoder is nothing but a simplified version of polar encoder and therefore can be pipelined implemented also. Moreover, a general approach which uniformly constructs most pipelined polar encoders via folding transformation is proposed. Implementation results have shown that both proposed pipelined polar encoder architectures achieve more than 98.3% complexity reduction and more than 9.86% speed-up compared to the conventional implementation.

Original languageEnglish
Title of host publication2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages3032-3035
Number of pages4
ISBN (Electronic)9781479983919
DOIs
Publication statusPublished - 27 Jul 2015
Externally publishedYes
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: 24 May 201527 May 2015

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2015-July
ISSN (Print)0271-4310

Conference

ConferenceIEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/TerritoryPortugal
CityLisbon
Period24/05/1527/05/15

Keywords

  • encoder
  • folding transformation
  • pipelined processing
  • Polar code

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