Performance-effective compaction of standard cell library for edge-triggered latches utilizing 0.5 micron technology

Chun Zhao*, W. Pan, C. Z. Zhao, K. L. Man, J. Choi, J. Chang

*Corresponding author for this work

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review


Very-Large-Scale Integration (VLSI) is the process of establishing integrated circuits. Although the process is getting more and more complex, the development of VLSI has effectively increased the design capability and system performance. Power dissipation for large and complex circuits has always been a concern for engineers on the leading edge of technology. This paper aims at establishing a new standard cell library. Moreover, the most relevant definitions, classifications and details (including power and performance optimization) of the new standard cell library are presented in this paper.

Original languageEnglish
Title of host publication2011 International SoC Design Conference, ISOCC 2011
PublisherIEEE Computer Society
Number of pages4
ISBN (Print)9781457707100
Publication statusPublished - 2011
Event8th International SoC Design Conference 2011, ISOCC 2011 - Jeju, Korea, Republic of
Duration: 17 Nov 201118 Nov 2011

Publication series

Name2011 International SoC Design Conference, ISOCC 2011


Conference8th International SoC Design Conference 2011, ISOCC 2011
Country/TerritoryKorea, Republic of


  • IC design
  • LVS
  • Layout
  • Standard cell library

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