Monolithic Dual-Gate E-Mode Device-Based NAND Logic Block for GaN MIS-HEMTs IC Platform

Yuhao Zhu; Fan Li; Miao Cui; Zhicheng Fang; Ang Li; Dongyi Yang; Yinchao Zhao; Huiqing Wen; Wen Liu

doi:10.1109/JEDS.2023.3265372

Monolithic Dual-Gate E-Mode Device-Based NAND Logic Block for GaN MIS-HEMTs IC Platform

Yuhao Zhu, Fan Li, Miao Cui, Zhicheng Fang, Ang Li, Dongyi Yang, Yinchao Zhao, Huiqing Wen, Wen Liu^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility-transistors) platform. The DG-NAND circuit has an area of 0.118 mm2 with the probe pad, which is 24% lower than the area of the DD-NAND circuit. Both static and dynamic experimental results validate the advantages of performance improvement of NAND circuits designed by dual-gate technology at an input voltage of 9 V. This paper demonstrates the design potential of dual-gate NAND in an all-GaN MIS-HEMTs platform through compact design.

Original language	English
Pages (from-to)	230-234
Number of pages	5
Journal	IEEE Journal of the Electron Devices Society
Volume	11
DOIs	https://doi.org/10.1109/JEDS.2023.3265372
Publication status	Published - 2023

Keywords

GaN
Logic circuits
MIS-HEMTs
dual-gate E-mode device
monolithic integration

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10.1109/JEDS.2023.3265372

Cite this

@article{ff62dc6fede045d7ae56f1e37b9a4737,

title = "Monolithic Dual-Gate E-Mode Device-Based NAND Logic Block for GaN MIS-HEMTs IC Platform",

abstract = "In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility-transistors) platform. The DG-NAND circuit has an area of 0.118 mm2 with the probe pad, which is 24% lower than the area of the DD-NAND circuit. Both static and dynamic experimental results validate the advantages of performance improvement of NAND circuits designed by dual-gate technology at an input voltage of 9 V. This paper demonstrates the design potential of dual-gate NAND in an all-GaN MIS-HEMTs platform through compact design.",

keywords = "GaN, Logic circuits, MIS-HEMTs, dual-gate E-mode device, monolithic integration",

author = "Yuhao Zhu and Fan Li and Miao Cui and Zhicheng Fang and Ang Li and Dongyi Yang and Yinchao Zhao and Huiqing Wen and Wen Liu",

note = "Publisher Copyright: {\textcopyright} 2013 IEEE.",

year = "2023",

doi = "10.1109/JEDS.2023.3265372",

language = "English",

volume = "11",

pages = "230--234",

journal = "IEEE Journal of the Electron Devices Society",

issn = "2168-6734",

}

TY - JOUR

T1 - Monolithic Dual-Gate E-Mode Device-Based NAND Logic Block for GaN MIS-HEMTs IC Platform

AU - Zhu, Yuhao

AU - Li, Fan

AU - Cui, Miao

AU - Fang, Zhicheng

AU - Li, Ang

AU - Yang, Dongyi

AU - Zhao, Yinchao

AU - Wen, Huiqing

AU - Liu, Wen

PY - 2023

Y1 - 2023

N2 - In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility-transistors) platform. The DG-NAND circuit has an area of 0.118 mm2 with the probe pad, which is 24% lower than the area of the DD-NAND circuit. Both static and dynamic experimental results validate the advantages of performance improvement of NAND circuits designed by dual-gate technology at an input voltage of 9 V. This paper demonstrates the design potential of dual-gate NAND in an all-GaN MIS-HEMTs platform through compact design.

AB - In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility-transistors) platform. The DG-NAND circuit has an area of 0.118 mm2 with the probe pad, which is 24% lower than the area of the DD-NAND circuit. Both static and dynamic experimental results validate the advantages of performance improvement of NAND circuits designed by dual-gate technology at an input voltage of 9 V. This paper demonstrates the design potential of dual-gate NAND in an all-GaN MIS-HEMTs platform through compact design.

KW - GaN

KW - Logic circuits

KW - MIS-HEMTs

KW - dual-gate E-mode device

KW - monolithic integration

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U2 - 10.1109/JEDS.2023.3265372

DO - 10.1109/JEDS.2023.3265372

M3 - Article

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SN - 2168-6734

VL - 11

SP - 230

EP - 234

JO - IEEE Journal of the Electron Devices Society

JF - IEEE Journal of the Electron Devices Society

ER -

Monolithic Dual-Gate E-Mode Device-Based NAND Logic Block for GaN MIS-HEMTs IC Platform

Abstract

Keywords

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