Modeling and verification of NCL circuits using PAT

Jieming Ma*, Ka Lok Man, Eng Gee Lim, Nan Zhang, Chi Un Lei, Sheng Uei Guan, Taikyeong Ted Jeong, Jong Kug Seon

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review


NULL Conventional Logic (NCL) is a Delay-Insensitive (DI) clockless paradigm and is suitable for implementing asynchronous circuits. Efficient methods of analysis are required to specify and verify such DI systems. Based on Delay Insensitive sequential Process (DISP) specification, this paper demonstrates the application of formal methods by applying Process Analysis Toolkit (PAT) to model and verify the behavior of NCL circuits. A few useful constructs are successfully modeled and verified by using PAT. The flexibility and simplicity of the coding, simulation and verification shows that PAT is effective and applicable for NCL circuit design and verification.

Original languageEnglish
Pages (from-to)3411-3415
Number of pages5
JournalProcedia Engineering
Publication statusPublished - 2011
Event2011 International Conference on Advanced in Control Engineering and Information Science, CEIS 2011 - Dali, Yunnam, China
Duration: 18 Aug 201119 Aug 2011


  • CSP#
  • NCL circuits
  • Specification
  • Verfication

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