TY - GEN
T1 - Low temperature selective Si and Si-based alloy epitaxy for advanced transistor applications
AU - Kim, Yihwan
AU - Zojaji, Ali
AU - Ye, Zhiyuan
AU - Lam, Andrew
AU - Dalida, Nicholas
AU - Sanchez, Errol
AU - Kuppurao, Satheesh
PY - 2006
Y1 - 2006
N2 - We have developed low temperature selective Si and Si-based alloy (SiGe and Si:C) epitaxy processes for advanced transistor fabrications. By lowering epitaxy process temperature (≤700°C), we have demonstrated elevated source/drain formation on ultra-thin (< 50 Å) body SOI transistors without Si agglomeration, smooth morphology of selective SiGe epitaxy with high [Ge] (>30 %) and [B] (>2E20 cm-3) concentrations, and selective Si:C epitaxy with high substitutional C concentration (>1 %). Also, we have increased growth rate of low temperature selective epitaxy processes by optimizing process parameters by adapting non-conventional deposition method.
AB - We have developed low temperature selective Si and Si-based alloy (SiGe and Si:C) epitaxy processes for advanced transistor fabrications. By lowering epitaxy process temperature (≤700°C), we have demonstrated elevated source/drain formation on ultra-thin (< 50 Å) body SOI transistors without Si agglomeration, smooth morphology of selective SiGe epitaxy with high [Ge] (>30 %) and [B] (>2E20 cm-3) concentrations, and selective Si:C epitaxy with high substitutional C concentration (>1 %). Also, we have increased growth rate of low temperature selective epitaxy processes by optimizing process parameters by adapting non-conventional deposition method.
UR - http://www.scopus.com/inward/record.url?scp=33846044272&partnerID=8YFLogxK
U2 - 10.1557/proc-0913-d04-05
DO - 10.1557/proc-0913-d04-05
M3 - Conference Proceeding
AN - SCOPUS:33846044272
SN - 1558998691
SN - 9781558998698
T3 - Materials Research Society Symposium Proceedings
SP - 125
EP - 130
BT - Transistor Scaling-Methods, Materials and Modeling
PB - Materials Research Society
T2 - 2006 MRS Spring Meeting
Y2 - 18 April 2006 through 19 April 2006
ER -