Low temperature selective Si and Si-based alloy epitaxy for advanced transistor applications

Yihwan Kim*, Ali Zojaji, Zhiyuan Ye, Andrew Lam, Nicholas Dalida, Errol Sanchez, Satheesh Kuppurao

*Corresponding author for this work

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

Abstract

We have developed low temperature selective Si and Si-based alloy (SiGe and Si:C) epitaxy processes for advanced transistor fabrications. By lowering epitaxy process temperature (≤700°C), we have demonstrated elevated source/drain formation on ultra-thin (< 50 Å) body SOI transistors without Si agglomeration, smooth morphology of selective SiGe epitaxy with high [Ge] (>30 %) and [B] (>2E20 cm-3) concentrations, and selective Si:C epitaxy with high substitutional C concentration (>1 %). Also, we have increased growth rate of low temperature selective epitaxy processes by optimizing process parameters by adapting non-conventional deposition method.

Original languageEnglish
Title of host publicationTransistor Scaling-Methods, Materials and Modeling
PublisherMaterials Research Society
Pages125-130
Number of pages6
ISBN (Print)1558998691, 9781558998698
DOIs
Publication statusPublished - 2006
Externally publishedYes
Event2006 MRS Spring Meeting - San Francisco, CA, United States
Duration: 18 Apr 200619 Apr 2006

Publication series

NameMaterials Research Society Symposium Proceedings
Volume913
ISSN (Print)0272-9172

Conference

Conference2006 MRS Spring Meeting
Country/TerritoryUnited States
CitySan Francisco, CA
Period18/04/0619/04/06

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