Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption

J. H. Kong, L. M. Ang, K. P. Seng, F. T. Ong

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

3 Citations (Scopus)

Abstract

This paper presents a low-complexity hardware design and implementation of the Skipjack algorithm using the Two Instruction Set Computer (TISC) on a Xilinx Spartan-3 FPGA. The proposed low-complexity design makes use of the TISC processor architecture with only Adder and XOR hardware ALU blocks to perform the complete Skipjack encryption onto plaintext data. The hardware architecture was verified using the Handel-C hardware description language uses only a single memory block RAM and only 129 instructions for a complete 32 rounds of encryption. The TISC Skipjack processor occupies only 1% of the Spartan-3 available chip area, which are 116 occupied slices in total, making it a suitable choice for implementation in sensor networks for embedded security where hardware resources are scarce.

Original languageEnglish
Title of host publicationInternational Conference on Information Networking 2011, ICOIN 2011
Pages472-477
Number of pages6
DOIs
Publication statusPublished - 2011
Externally publishedYes
EventInternational Conference on Information Networking 2011, ICOIN 2011 - Kuala Lumpur, Malaysia
Duration: 26 Jan 201128 Jan 2011

Publication series

NameInternational Conference on Information Networking 2011, ICOIN 2011

Conference

ConferenceInternational Conference on Information Networking 2011, ICOIN 2011
Country/TerritoryMalaysia
CityKuala Lumpur
Period26/01/1128/01/11

Keywords

  • Skipjack
  • TISC
  • Two instruction set computer
  • WSN
  • Wireless sensor network

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