@inproceedings{1b0d8828ad8340d4be178fcfd2a9d660,
title = "High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology",
abstract = "Estimating arithmetic is a design paradigm for DSP hardware. By allowing structurally incomplete arithmetic circuits to occasionally perform imprecise calculations, higher performance can be achieved in many different electronic systems. By means of approximate compressor design and bottom-up tree topology, this paper presents a novel approach of implementing high-speed, area-efficient and power-aware multipliers. Experimental results are given to show the applicability and effectiveness of our proposed approach.",
keywords = "compressors, computer arithmetic, estimating arithmetic, multipliers",
author = "Jieming Ma and Man, {Ka Lok} and Nan Zhang and Guan, {Sheng Uei} and Jeong, {Taikyeong Ted}",
year = "2013",
doi = "10.1117/12.2014353",
language = "English",
isbn = "9780819495884",
series = "Proceedings of SPIE - The International Society for Optical Engineering",
publisher = "SPIE",
booktitle = "Fifth International Conference on Machine Vision, ICMV 2012",
note = "2012 5th International Conference on Machine Vision: Algorithms, Pattern Recognition and Basic Technologies, ICMV 2012 ; Conference date: 20-10-2012 Through 21-10-2012",
}