High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology

Jieming Ma, Ka Lok Man, Nan Zhang, Sheng Uei Guan, Taikyeong Ted Jeong

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

2 Citations (Scopus)

Abstract

Estimating arithmetic is a design paradigm for DSP hardware. By allowing structurally incomplete arithmetic circuits to occasionally perform imprecise calculations, higher performance can be achieved in many different electronic systems. By means of approximate compressor design and bottom-up tree topology, this paper presents a novel approach of implementing high-speed, area-efficient and power-aware multipliers. Experimental results are given to show the applicability and effectiveness of our proposed approach.

Original languageEnglish
Title of host publicationFifth International Conference on Machine Vision, ICMV 2012
Subtitle of host publicationAlgorithms, Pattern Recognition and Basic Technologies
PublisherSPIE
ISBN (Print)9780819495884
DOIs
Publication statusPublished - 2013
Event2012 5th International Conference on Machine Vision: Algorithms, Pattern Recognition and Basic Technologies, ICMV 2012 - Wuhan, China
Duration: 20 Oct 201221 Oct 2012

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
Volume8784
ISSN (Print)0277-786X
ISSN (Electronic)1996-756X

Conference

Conference2012 5th International Conference on Machine Vision: Algorithms, Pattern Recognition and Basic Technologies, ICMV 2012
Country/TerritoryChina
CityWuhan
Period20/10/1221/10/12

Keywords

  • compressors
  • computer arithmetic
  • estimating arithmetic
  • multipliers

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