Enabling hetero-integration of III-V and Ge-based transistors on silicon with ultra-thin buffers formed by interfacial misfit technique

Xiao Gong, Sachin Yadav, Kian Hui Goh, Kian Hua Tan, Annie, Kian Lu Low, Bowen Jia, Soon Fatt Yoon, Gengchiau Liang, Yee Chia Yeo

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

Abstract

In this paper, we discuss the application of the interfacial misfit (IMF) technique to enable the heterogeneous integration of III-V and Ge-based transistors on Si substrates. Ge pFETs and InAs nFETs were co-integrated on a Si substrate using common contact formation, digital etch, and gate stack formation modules. In addition, vertically stacked nanowire (NW) GaSb pFETs and InAs nFETs on Si substrates were also realized.

Original languageEnglish
Title of host publicationSiGe, Ge, and Related Materials
Subtitle of host publicationMaterials, Processing, and Devices 7
EditorsJ. Murota, B. Tillack, M. Caymax, G. Masini, D. L. Harame, S. Miyazaki
PublisherElectrochemical Society Inc.
Pages421-437
Number of pages17
Edition8
ISBN (Electronic)9781607685395
DOIs
Publication statusPublished - 2016
Externally publishedYes
EventSymposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting - Honolulu, United States
Duration: 2 Oct 20167 Oct 2016

Publication series

NameECS Transactions
Number8
Volume75
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Conference

ConferenceSymposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting
Country/TerritoryUnited States
CityHonolulu
Period2/10/167/10/16

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