Effects of layout methods of RF CMOS on noise performance

Wen Wu*, Sang Lam, Mansun Chan

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

13 Citations (Scopus)


This paper presents a study on the effects of different layout methods on the noise performance of RF CMOS transistors. The optimization of RF characteristics using multifinger layout and a more compact waffle layout with Manhattan-oriented polysilicon gate are studied. The waffle layout is demonstrated to have a larger design window through the simulation as well as the experimental data. The improvement of both the maximum oscillation frequency fmax and the cutoff frequency fT at the same biasing condition leads to the improvement on RF noise performance for the waffle MOSFETs. Compared with the multifinger devices, the SpectreRF simulation reveals that 10% reduction in noise figure is achieved when the waffle MOSFETs are used in CMOS low-noise amplifiers.

Original languageEnglish
Pages (from-to)2753-2759
Number of pages7
JournalIEEE Transactions on Electron Devices
Issue number12
Publication statusPublished - Dec 2005
Externally publishedYes


  • Cutoff frequency
  • Layout
  • Maximum oscillation frequency
  • Noise
  • Radio frequency (RF)

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