Development of high growth rate selective silicon epitaxy at low substrate temperatures for dram elevated Source/Drain application

Elevated Source/Drain device structures by selective epitaxial thin-film deposition have become industry standard for advanced nanoelectronics fabrication in both logic and memory applications. In this paper, a novel filmgrowth approach of selective silicon epitaxy for the DRAM application is presented. Regarding the selective process on a substrate patterned with dielectric films, deposition of single-crystal silicon takes place only on the exposed substrate areas but no film nucleation or growth occurs on the dielectric areas. Conventionally such process is controlled by mixing a deposition silicon source (e.g., DCS, SiH₄) with an etchant gas such as HCl where film growth and film etching/suppression occur simultaneously. Unfortunately, the growth rate via such chemistries is severely hammered and thus becomes not worthy for production at process temperatures less than 800d̀C. We have developed an alternative method where the growth and etching reactions are separated and optimized individually. The key feature of this new approach is to utilize the combination of modulating all process parameters: i) reactor pressure, ii) substrate temperature, and iii) gas-flow distribution of deposition and etchant sources in a series of alternating deposition and etching cycles. Silicon nuclei formation on the dielectric surface is suppressed below their critical sizes while epitaxial growth is maximized on the exposed silicon areas. As a result, high selective growth rates of a factor of >2 are obtained at 700-750d̀C comparing to the conventional deposition and this development extends the process to future technology nodes that demand lower thermal budgets to continue device scaling.