Design of a reliable XOR-XNOR circuit for arithmetic logic units

Mouna Karmani*, Chiraz Khedhiri, Belgacem Hamdi, Amir Mohammad Rahmani, Ka Lok Man, Kaiyu Wan

*Corresponding author for this work

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review


Computer systems used in safety-critical applications like space, avionic and biomedical applications require high reliable integrated circuits (ICs) to ensure the accuracy of data they process. As Arithmetic Logic Units (ALUs) are essential element of computers, designing reliable ALUs is becoming an appropriate strategy to design fault-tolerant computers. In fact, with the continuous increase of integration densities and complexities ICs are susceptible to many modes of failure. Thereby, Reliable operation of ALUs is critical for high performance safety-critical computers. Given that XOR-XNOR circuits are basic building blocks in ALUs, designing efficient reliable XOR-XNOR gates is an important challenge in the area of high performance computers. The reliability enhancement technique presented in this work is based on using a Concurrent Error Detection (CED) based reliable XOR-XNOR circuit implementation to detect permanent and transient faults in ALUs during normal operation in order to improve the reliability of highly critical computer systems. The proposed design is performed using the 32 nm process technology.

Original languageEnglish
Title of host publicationNetwork and Parallel Computing - 9th IFIP International Conference, NPC 2012, Proceedings
Number of pages8
Publication statusPublished - 2012
Event9th IFIP International Conference on Network and Parallel Computing, NPC 2012 - Gwangju, Korea, Republic of
Duration: 6 Sept 20128 Sept 2012

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume7513 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Conference9th IFIP International Conference on Network and Parallel Computing, NPC 2012
Country/TerritoryKorea, Republic of


  • Concurrent error detection
  • Fault model
  • Fault-secure property
  • Self-testing property
  • XOR-XNOR circuits

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