Comparative analysis and parameter extraction of enhanced waffle MOSFET

Wen Wu; Sang Lam; Ping K. Ko; Mansun Chan

doi:10.1109/EDSSC.2003.1283512

Comparative analysis and parameter extraction of enhanced waffle MOSFET

Wen Wu, Sang Lam, Ping K. Ko, Mansun Chan

Hong Kong University of Science and Technology

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

4 Citations (Scopus)

Abstract

Unlike the traditional layout strategy in which large size transistors were fabricated by increasing the number of parallel polysilicon gates, waffle MOSFET with a novel structure is introduced due to its excellent expansibility and area efficiency. In this work a compact waffle MOSFET using an enhanced waffle-layout strategy is presented. Comparisons are made on two different layout implementations of wide transistors with the same dimensions using a standard 0.35-μm CMOS technology. With the proposed accurate model suitable to waffle MOSFET the small signal parameters are extracted and the experimental results demonstrate the benefits of waffle layout without any extra processing cost.

Original language	English
Title of host publication	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	193-196
Number of pages	4
ISBN (Electronic)	0780377494, 9780780377493
DOIs	https://doi.org/10.1109/EDSSC.2003.1283512
Publication status	Published - 2003
Externally published	Yes
Event	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong Duration: 16 Dec 2003 → 18 Dec 2003

Publication series

Name	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Conference

Conference	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Country/Territory	Hong Kong
City	Tsimshatsui, Kowloon
Period	16/12/03 → 18/12/03

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10.1109/EDSSC.2003.1283512

Cite this

Wu, W., Lam, S., Ko, P. K., & Chan, M. (2003). Comparative analysis and parameter extraction of enhanced waffle MOSFET. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 (pp. 193-196). Article 1283512 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2003.1283512

@inproceedings{8ef7ccd051f9420da69826837a36f199,

title = "Comparative analysis and parameter extraction of enhanced waffle MOSFET",

abstract = "Unlike the traditional layout strategy in which large size transistors were fabricated by increasing the number of parallel polysilicon gates, waffle MOSFET with a novel structure is introduced due to its excellent expansibility and area efficiency. In this work a compact waffle MOSFET using an enhanced waffle-layout strategy is presented. Comparisons are made on two different layout implementations of wide transistors with the same dimensions using a standard 0.35-μm CMOS technology. With the proposed accurate model suitable to waffle MOSFET the small signal parameters are extracted and the experimental results demonstrate the benefits of waffle layout without any extra processing cost.",

author = "Wen Wu and Sang Lam and Ko, {Ping K.} and Mansun Chan",

note = "Publisher Copyright: {\textcopyright}2003 IEEE.; IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 ; Conference date: 16-12-2003 Through 18-12-2003",

year = "2003",

doi = "10.1109/EDSSC.2003.1283512",

language = "English",

series = "2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "193--196",

booktitle = "2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003",

}

Wu, W, Lam, S, Ko, PK & Chan, M 2003, Comparative analysis and parameter extraction of enhanced waffle MOSFET. in 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003., 1283512, 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 193-196, IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Tsimshatsui, Kowloon, Hong Kong, 16/12/03. https://doi.org/10.1109/EDSSC.2003.1283512

Comparative analysis and parameter extraction of enhanced waffle MOSFET. / Wu, Wen; Lam, Sang; Ko, Ping K. et al.
2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 193-196 1283512 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

TY - GEN

T1 - Comparative analysis and parameter extraction of enhanced waffle MOSFET

AU - Wu, Wen

AU - Lam, Sang

AU - Ko, Ping K.

AU - Chan, Mansun

PY - 2003

Y1 - 2003

N2 - Unlike the traditional layout strategy in which large size transistors were fabricated by increasing the number of parallel polysilicon gates, waffle MOSFET with a novel structure is introduced due to its excellent expansibility and area efficiency. In this work a compact waffle MOSFET using an enhanced waffle-layout strategy is presented. Comparisons are made on two different layout implementations of wide transistors with the same dimensions using a standard 0.35-μm CMOS technology. With the proposed accurate model suitable to waffle MOSFET the small signal parameters are extracted and the experimental results demonstrate the benefits of waffle layout without any extra processing cost.

AB - Unlike the traditional layout strategy in which large size transistors were fabricated by increasing the number of parallel polysilicon gates, waffle MOSFET with a novel structure is introduced due to its excellent expansibility and area efficiency. In this work a compact waffle MOSFET using an enhanced waffle-layout strategy is presented. Comparisons are made on two different layout implementations of wide transistors with the same dimensions using a standard 0.35-μm CMOS technology. With the proposed accurate model suitable to waffle MOSFET the small signal parameters are extracted and the experimental results demonstrate the benefits of waffle layout without any extra processing cost.

UR - http://www.scopus.com/inward/record.url?scp=29044445494&partnerID=8YFLogxK

U2 - 10.1109/EDSSC.2003.1283512

DO - 10.1109/EDSSC.2003.1283512

M3 - Conference Proceeding

AN - SCOPUS:29044445494

T3 - 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

SP - 193

EP - 196

BT - 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Y2 - 16 December 2003 through 18 December 2003

ER -

Wu W, Lam S, Ko PK, Chan M. Comparative analysis and parameter extraction of enhanced waffle MOSFET. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 193-196. 1283512. (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003). doi: 10.1109/EDSSC.2003.1283512

Comparative analysis and parameter extraction of enhanced waffle MOSFET

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