Comparative analysis and parameter extraction of enhanced waffle MOSFET

Wen Wu, Sang Lam, Ping K. Ko, Mansun Chan

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

4 Citations (Scopus)

Abstract

Unlike the traditional layout strategy in which large size transistors were fabricated by increasing the number of parallel polysilicon gates, waffle MOSFET with a novel structure is introduced due to its excellent expansibility and area efficiency. In this work a compact waffle MOSFET using an enhanced waffle-layout strategy is presented. Comparisons are made on two different layout implementations of wide transistors with the same dimensions using a standard 0.35-μm CMOS technology. With the proposed accurate model suitable to waffle MOSFET the small signal parameters are extracted and the experimental results demonstrate the benefits of waffle layout without any extra processing cost.

Original languageEnglish
Title of host publication2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages193-196
Number of pages4
ISBN (Electronic)0780377494, 9780780377493
DOIs
Publication statusPublished - 2003
Externally publishedYes
EventIEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong
Duration: 16 Dec 200318 Dec 2003

Publication series

Name2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Conference

ConferenceIEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Country/TerritoryHong Kong
CityTsimshatsui, Kowloon
Period16/12/0318/12/03

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