An efficient hardware architecture for multilayer spiking neural networks

Yuling Luo; Lei Wan; Junxiu Liu; Jinlei Zhang; Yi Cao

doi:10.1007/978-3-319-70136-3_83

An efficient hardware architecture for multilayer spiking neural networks

Yuling Luo, Lei Wan, Junxiu Liu^*, Jinlei Zhang, Yi Cao

^*Corresponding author for this work

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

1 Citation (Scopus)

Abstract

Spiking Neural Network (SNN) is the most recent computational model that can emulate the behaviors of biological neuron system. This paper highlights and discusses an efficient hardware architecture for the hardware SNNs, which includes a layer-level tile architecture (LTA) for the neurons and synapses, and a novel routing architecture (NRA) for the interconnections between the neuron nodes. In addition, a visualization performance monitoring platform is designed, which is used as functional verification and performance monitoring for the SNN hardware system. Experimental results demonstrate that the proposed architecture is feasible and capable of scaling to large hardware multilayer SNNs.

Original language	English
Title of host publication	Neural Information Processing - 24th International Conference, ICONIP 2017, Proceedings
Editors	Derong Liu, Shengli Xie, Dongbin Zhao, Yuanqing Li, El-Sayed M. El-Alfy
Publisher	Springer Verlag
Pages	786-795
Number of pages	10
ISBN (Print)	9783319701356
DOIs	https://doi.org/10.1007/978-3-319-70136-3_83
Publication status	Published - 2017
Externally published	Yes
Event	24th International Conference on Neural Information Processing, ICONIP 2017 - Guangzhou, China Duration: 14 Nov 2017 → 18 Nov 2017

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	10639 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	24th International Conference on Neural Information Processing, ICONIP 2017
Country/Territory	China
City	Guangzhou
Period	14/11/17 → 18/11/17

Keywords

FPGA
Hardware architecture
Spiking neural networks

Access to Document

10.1007/978-3-319-70136-3_83

Cite this

Luo, Y., Wan, L., Liu, J., Zhang, J., & Cao, Y. (2017). An efficient hardware architecture for multilayer spiking neural networks. In D. Liu, S. Xie, D. Zhao, Y. Li, & E.-S. M. El-Alfy (Eds.), Neural Information Processing - 24th International Conference, ICONIP 2017, Proceedings (pp. 786-795). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 10639 LNCS). Springer Verlag. https://doi.org/10.1007/978-3-319-70136-3_83

Luo, Yuling ; Wan, Lei ; Liu, Junxiu et al. / An efficient hardware architecture for multilayer spiking neural networks. Neural Information Processing - 24th International Conference, ICONIP 2017, Proceedings. editor / Derong Liu ; Shengli Xie ; Dongbin Zhao ; Yuanqing Li ; El-Sayed M. El-Alfy. Springer Verlag, 2017. pp. 786-795 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{d6dd80ac146f49ee8ed7c2d70741d952,

title = "An efficient hardware architecture for multilayer spiking neural networks",

abstract = "Spiking Neural Network (SNN) is the most recent computational model that can emulate the behaviors of biological neuron system. This paper highlights and discusses an efficient hardware architecture for the hardware SNNs, which includes a layer-level tile architecture (LTA) for the neurons and synapses, and a novel routing architecture (NRA) for the interconnections between the neuron nodes. In addition, a visualization performance monitoring platform is designed, which is used as functional verification and performance monitoring for the SNN hardware system. Experimental results demonstrate that the proposed architecture is feasible and capable of scaling to large hardware multilayer SNNs.",

keywords = "FPGA, Hardware architecture, Spiking neural networks",

author = "Yuling Luo and Lei Wan and Junxiu Liu and Jinlei Zhang and Yi Cao",

note = "Publisher Copyright: {\textcopyright} Springer International Publishing AG 2017.; 24th International Conference on Neural Information Processing, ICONIP 2017 ; Conference date: 14-11-2017 Through 18-11-2017",

year = "2017",

doi = "10.1007/978-3-319-70136-3_83",

language = "English",

isbn = "9783319701356",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

publisher = "Springer Verlag",

pages = "786--795",

editor = "Derong Liu and Shengli Xie and Dongbin Zhao and Yuanqing Li and El-Alfy, {El-Sayed M.}",

booktitle = "Neural Information Processing - 24th International Conference, ICONIP 2017, Proceedings",

}

Luo, Y, Wan, L, Liu, J, Zhang, J & Cao, Y 2017, An efficient hardware architecture for multilayer spiking neural networks. in D Liu, S Xie, D Zhao, Y Li & E-SM El-Alfy (eds), Neural Information Processing - 24th International Conference, ICONIP 2017, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 10639 LNCS, Springer Verlag, pp. 786-795, 24th International Conference on Neural Information Processing, ICONIP 2017, Guangzhou, China, 14/11/17. https://doi.org/10.1007/978-3-319-70136-3_83

An efficient hardware architecture for multilayer spiking neural networks. / Luo, Yuling; Wan, Lei; Liu, Junxiu et al.
Neural Information Processing - 24th International Conference, ICONIP 2017, Proceedings. ed. / Derong Liu; Shengli Xie; Dongbin Zhao; Yuanqing Li; El-Sayed M. El-Alfy. Springer Verlag, 2017. p. 786-795 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 10639 LNCS).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

TY - GEN

T1 - An efficient hardware architecture for multilayer spiking neural networks

AU - Luo, Yuling

AU - Wan, Lei

AU - Liu, Junxiu

AU - Zhang, Jinlei

AU - Cao, Yi

N1 - Publisher Copyright: © Springer International Publishing AG 2017.

PY - 2017

Y1 - 2017

N2 - Spiking Neural Network (SNN) is the most recent computational model that can emulate the behaviors of biological neuron system. This paper highlights and discusses an efficient hardware architecture for the hardware SNNs, which includes a layer-level tile architecture (LTA) for the neurons and synapses, and a novel routing architecture (NRA) for the interconnections between the neuron nodes. In addition, a visualization performance monitoring platform is designed, which is used as functional verification and performance monitoring for the SNN hardware system. Experimental results demonstrate that the proposed architecture is feasible and capable of scaling to large hardware multilayer SNNs.

AB - Spiking Neural Network (SNN) is the most recent computational model that can emulate the behaviors of biological neuron system. This paper highlights and discusses an efficient hardware architecture for the hardware SNNs, which includes a layer-level tile architecture (LTA) for the neurons and synapses, and a novel routing architecture (NRA) for the interconnections between the neuron nodes. In addition, a visualization performance monitoring platform is designed, which is used as functional verification and performance monitoring for the SNN hardware system. Experimental results demonstrate that the proposed architecture is feasible and capable of scaling to large hardware multilayer SNNs.

KW - FPGA

KW - Hardware architecture

KW - Spiking neural networks

UR - http://www.scopus.com/inward/record.url?scp=85035141246&partnerID=8YFLogxK

U2 - 10.1007/978-3-319-70136-3_83

DO - 10.1007/978-3-319-70136-3_83

M3 - Conference Proceeding

AN - SCOPUS:85035141246

SN - 9783319701356

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 786

EP - 795

BT - Neural Information Processing - 24th International Conference, ICONIP 2017, Proceedings

A2 - Liu, Derong

A2 - Xie, Shengli

A2 - Zhao, Dongbin

A2 - Li, Yuanqing

A2 - El-Alfy, El-Sayed M.

PB - Springer Verlag

T2 - 24th International Conference on Neural Information Processing, ICONIP 2017

Y2 - 14 November 2017 through 18 November 2017

ER -

Luo Y, Wan L, Liu J, Zhang J, Cao Y. An efficient hardware architecture for multilayer spiking neural networks. In Liu D, Xie S, Zhao D, Li Y, El-Alfy ESM, editors, Neural Information Processing - 24th International Conference, ICONIP 2017, Proceedings. Springer Verlag. 2017. p. 786-795. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-319-70136-3_83

An efficient hardware architecture for multilayer spiking neural networks

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this