Algebra-logical diagnosis model for SoC F-IP

Vladimir Hahanov; Vladimir Obrizan; Eugenia Litvinova; Ka Lok Man

Algebra-logical diagnosis model for SoC F-IP

Vladimir Hahanov^*, Vladimir Obrizan, Eugenia Litvinova, Ka Lok Man

^*Corresponding author for this work

Kharkiv National University of Radio Electronics

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

Algebra-logical model, method and algorithm of fault embedded diagnosis in functional blocks of SoC are proposed. The reduced SoC Functional Intellectual Property Infrastructure that is characterized by minimal set of the embedded diagnosis processes in real time and enables to realize the services: testing of the nominal functions on basis of generable input patterns and analysis of output reactions; fault diagnosis with given resolution of fault location by means of utilization of the IEEE 1500 multiprobe; fault simulation to provide of realization of the first two procedures on basis of the fault detection table is presented.

Original language	English
Pages (from-to)	708-717
Number of pages	10
Journal	WSEAS Transactions on Circuits and Systems
Volume	7
Issue number	7
Publication status	Published - 2008
Externally published	Yes

Keywords

Diagnosis
Electronic system level
Fault
Functional intellectual property
Infrastructure intellectual property
System-on-Chip
Testbeneh
Transaction level modelling

Cite this

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title = "Algebra-logical diagnosis model for SoC F-IP",

abstract = "Algebra-logical model, method and algorithm of fault embedded diagnosis in functional blocks of SoC are proposed. The reduced SoC Functional Intellectual Property Infrastructure that is characterized by minimal set of the embedded diagnosis processes in real time and enables to realize the services: testing of the nominal functions on basis of generable input patterns and analysis of output reactions; fault diagnosis with given resolution of fault location by means of utilization of the IEEE 1500 multiprobe; fault simulation to provide of realization of the first two procedures on basis of the fault detection table is presented.",

keywords = "Diagnosis, Electronic system level, Fault, Functional intellectual property, Infrastructure intellectual property, System-on-Chip, Testbeneh, Transaction level modelling",

author = "Vladimir Hahanov and Vladimir Obrizan and Eugenia Litvinova and Man, {Ka Lok}",

year = "2008",

language = "English",

volume = "7",

pages = "708--717",

journal = "WSEAS Transactions on Circuits and Systems",

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TY - JOUR

T1 - Algebra-logical diagnosis model for SoC F-IP

AU - Hahanov, Vladimir

AU - Obrizan, Vladimir

AU - Litvinova, Eugenia

AU - Man, Ka Lok

PY - 2008

Y1 - 2008

N2 - Algebra-logical model, method and algorithm of fault embedded diagnosis in functional blocks of SoC are proposed. The reduced SoC Functional Intellectual Property Infrastructure that is characterized by minimal set of the embedded diagnosis processes in real time and enables to realize the services: testing of the nominal functions on basis of generable input patterns and analysis of output reactions; fault diagnosis with given resolution of fault location by means of utilization of the IEEE 1500 multiprobe; fault simulation to provide of realization of the first two procedures on basis of the fault detection table is presented.

AB - Algebra-logical model, method and algorithm of fault embedded diagnosis in functional blocks of SoC are proposed. The reduced SoC Functional Intellectual Property Infrastructure that is characterized by minimal set of the embedded diagnosis processes in real time and enables to realize the services: testing of the nominal functions on basis of generable input patterns and analysis of output reactions; fault diagnosis with given resolution of fault location by means of utilization of the IEEE 1500 multiprobe; fault simulation to provide of realization of the first two procedures on basis of the fault detection table is presented.

KW - Diagnosis

KW - Electronic system level

KW - Fault

KW - Functional intellectual property

KW - Infrastructure intellectual property

KW - System-on-Chip

KW - Testbeneh

KW - Transaction level modelling

UR - http://www.scopus.com/inward/record.url?scp=59249083556&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:59249083556

SN - 1109-2734

VL - 7

SP - 708

EP - 717

JO - WSEAS Transactions on Circuits and Systems

JF - WSEAS Transactions on Circuits and Systems

IS - 7

ER -

Algebra-logical diagnosis model for SoC F-IP

Abstract

Keywords

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