Abstract
Algebra-logical model, method and algorithm of fault embedded diagnosis in functional blocks of SoC are proposed. The reduced SoC Functional Intellectual Property Infrastructure that is characterized by minimal set of the embedded diagnosis processes in real time and enables to realize the services: testing of the nominal functions on basis of generable input patterns and analysis of output reactions; fault diagnosis with given resolution of fault location by means of utilization of the IEEE 1500 multiprobe; fault simulation to provide of realization of the first two procedures on basis of the fault detection table is presented.
Original language | English |
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Pages (from-to) | 708-717 |
Number of pages | 10 |
Journal | WSEAS Transactions on Circuits and Systems |
Volume | 7 |
Issue number | 7 |
Publication status | Published - 2008 |
Externally published | Yes |
Keywords
- Diagnosis
- Electronic system level
- Fault
- Functional intellectual property
- Infrastructure intellectual property
- System-on-Chip
- Testbeneh
- Transaction level modelling