Algebra-logical diagnosis model for SoC F-IP

Vladimir Hahanov*, Vladimir Obrizan, Eugenia Litvinova, Ka Lok Man

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


Algebra-logical model, method and algorithm of fault embedded diagnosis in functional blocks of SoC are proposed. The reduced SoC Functional Intellectual Property Infrastructure that is characterized by minimal set of the embedded diagnosis processes in real time and enables to realize the services: testing of the nominal functions on basis of generable input patterns and analysis of output reactions; fault diagnosis with given resolution of fault location by means of utilization of the IEEE 1500 multiprobe; fault simulation to provide of realization of the first two procedures on basis of the fault detection table is presented.

Original languageEnglish
Pages (from-to)708-717
Number of pages10
JournalWSEAS Transactions on Circuits and Systems
Issue number7
Publication statusPublished - 2008
Externally publishedYes


  • Diagnosis
  • Electronic system level
  • Fault
  • Functional intellectual property
  • Infrastructure intellectual property
  • System-on-Chip
  • Testbeneh
  • Transaction level modelling

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