TY - GEN
T1 - A semi-folded decoding architecture for flexible codeword length configuration of polar codes
AU - Cao, Shan
AU - Jiang, Limin
AU - Lin, Ting
AU - Zhang, Shunqing
AU - Xu, Shugong
N1 - Publisher Copyright:
© 2021 IEEE
PY - 2021
Y1 - 2021
N2 - Diverse application scenarios in 5G and beyond wireless communication systems have introduced various requirements in code lengths and rates of channel codes. For the decoding of polar codes, especially the belief-propagation (BP) decoding, flexible configuration of codeword length is still not involved in current decoders. In this paper, a semi-folded decoding structure is proposed which can be reconfigured to support multiple codeword lengths. Up to 16 codes can be decoded in parallel and the utilization of processing units is no less than 87.5% for various codeword lengths. The peak throughput of 19.29 Gbps can be achieved by the proposed decoder in SMIC 55 nm CMOS technology.
AB - Diverse application scenarios in 5G and beyond wireless communication systems have introduced various requirements in code lengths and rates of channel codes. For the decoding of polar codes, especially the belief-propagation (BP) decoding, flexible configuration of codeword length is still not involved in current decoders. In this paper, a semi-folded decoding structure is proposed which can be reconfigured to support multiple codeword lengths. Up to 16 codes can be decoded in parallel and the utilization of processing units is no less than 87.5% for various codeword lengths. The peak throughput of 19.29 Gbps can be achieved by the proposed decoder in SMIC 55 nm CMOS technology.
KW - Belief Propagation (BP)
KW - Hardware implementation
KW - Polar codes
UR - http://www.scopus.com/inward/record.url?scp=85109010200&partnerID=8YFLogxK
U2 - 10.1109/ISCAS51556.2021.9401424
DO - 10.1109/ISCAS51556.2021.9401424
M3 - Conference Proceeding
AN - SCOPUS:85109010200
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Y2 - 22 May 2021 through 28 May 2021
ER -