A design for testability approach for nano-CMOS analogue integrated circuits

Mouna Karmani*, Chiraz Khedhiri, Belgacem Hamdi, Ka Lok Man, Rached Tourki

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). This article presents two designs for testability and fault diagnosis techniques using a new design analogue checker circuit in order to improve the testability and the diagnosability of nano-CMOS (complementary metal oxide semiconductor) analogue circuits used in safety-critical applications based on the system-on-chip (SoC) approach design. The testing techniques presented in this work can be done during and after the system fabrication. The checker is implemented in full-custom 65 nm Complementary metal-oxide-semiconductor (CMOS) technology with low supply voltage and small-size capabilities. SPICE simulations of the post-layout extracted CMOS checker, which include all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checker.

Original languageEnglish
Pages (from-to)837-850
Number of pages14
JournalInternational Journal of Electronics
Issue number6
Publication statusPublished - 1 Jun 2013


  • DfT
  • amplitude fluctuation
  • analogue integrated circuits
  • checker
  • fault
  • nano-CMOS technology
  • testing


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